11Electrical and Computer EngineeringCPE/EE 422/522Spring 2004Chapter 10 - Hardware Testing andDesign for TestabilityDr. Rhonda Kay GaedeUAHElectrical and Computer EngineeringSpring 2004 Slide #2UAH CPE/EE 422/522Chapter 10Motivation for Testing¥ Testing during design process—use VHDL test benches to verify thatthe _______________________ used are correct—verify _____________ after synthesis¥ Post-fabrication testing—when a digital system is manufactured,test to verify that it is free from ___________________________—today, cost of testing is _______ component of themanufacturing cost—efficient techniques are needed to test anddesign digital systems so that they are easy to test2Electrical and Computer EngineeringSpring 2004 Slide #3UAH CPE/EE 422/522Chapter 1010.1 Testing Combinational Logic¥ Common types of errors—___________—___________¥ If the input to a gate is shorted to ground,the input acts as if it is stuck at _______—s-a-0 (stuck-at-0) faults¥ If the input to a gate is shorted to positivesupply voltage, the input acts as if it is stuckat _______—s-a-1 (stuck-at-1) faultsElectrical and Computer EngineeringSpring 2004 Slide #4UAH CPE/EE 422/522Chapter 1010.1 Testing Combinational Logic -Stuck-at Faults¥ How many single stuck-at faults —_______ where n is the number of inputs¥ We will assume—that there is _________________ active at a timein the whole circuit— SSF single stuck-at faults-a-0s-a-0s-a-0s-a-1s-a-1s-a-13Electrical and Computer EngineeringSpring 2004 Slide #5UAH CPE/EE 422/522Chapter 1010.1 Testing Combinational Logic -Stuck-at Faults for AND and OR gatesTest afor s-a-0Test afor s-a-1Test afor s-a-1Test afor s-a-0Electrical and Computer EngineeringSpring 2004 Slide #6UAH CPE/EE 422/522Chapter 1010.1 Testing Combinational Logic -Testing an AND-OR NetworkBRUTE-FORCE testing:apply 29=512 different inputcombinations and check the output4Electrical and Computer EngineeringSpring 2004 Slide #7UAH CPE/EE 422/522Chapter 1010.1 Testing Combinational Logic -Path Sensitization ExampleTest n to s-a-1We can test a, m, n, or p to s-a-0Change a to 1 =>Testing internal faults:choose a set of inputs that will excite the fault andthen propagate the fault to the network outputElectrical and Computer EngineeringSpring 2004 Slide #8UAH CPE/EE 422/522Chapter 1010.1 Testing Combinational Logic -Obtaining a Test Set¥ What is a minimum set of test vectors to test thenetwork below for all stuck-at-1 and stuck-at-0 faults?Start with A-a-p-v-f-F path, determine the test vector to test s-a-0determine the list of faults coveredselect an untested fault, determine the required ABCD inputsdetermine the additional faults testedrepeat the process until all faults are covered5Electrical and Computer EngineeringSpring 2004 Slide #9UAH CPE/EE 422/522Chapter 1010.1 Testing Combinational Logic -Obtaining a Test Set (continued)¥ Step 1: A-a-p-v-f-F, s-a-0— ABCD: 1101 (+)¥ Step 2: s-a-0 for c— C=1, p=0, w=1 => ABCD=1011 (*)¥ Step 3: s-a-0 for q— C=1, D=1, t=0, s=1 => ABCD=1111 (#)¥ Step 4: s-a-1 for a—A=0, B=1, C=0, D=1 => ABCD=0101 (&)¥ Step 5: s-a-1 for d (%)— D=0, C =0, t=1 => ABCD = 1100#+f#+w&+v#+u#*t*#s#+r+#q*+p%+d&*c*+b&+a10Electrical and Computer EngineeringSpring 2004 Slide #10UAH CPE/EE 422/522Chapter 1010.2 Testing Sequential Logic¥ In general, much more difficult than testing combinational logicsince we must use ________________— typically we can observe inputs and outputs,not the ________________— assume the ______ input,so we can reset the network to the ____________¥ Test procedure— reset the network to the initial state— apply a test sequence and observe the output sequence— if the output is correct, repeat the test for another sequence¥ How many test sequences do we have?— how do we test that the initial state of the network under testis equivalent to the initial state of the correct network?— what is the sequence length?6Electrical and Computer EngineeringSpring 2004 Slide #11UAH CPE/EE 422/522Chapter 1010.2 Testing Sequential Logic -Magnitude of the Problem¥ In practice, if the networkhas N or fewer states, thenapply only input sequencesof length less than or equal2N-1¥Example— consider a network whichincludes 5 inputs, 1 output,and 4 states— total number of testsequences: (25)7 = 235 =>infeasible (!)— derive a small set of testsequences that willadequately test a SNElectrical and Computer EngineeringSpring 2004 Slide #12UAH CPE/EE 422/522Chapter 1010.2 Testing Sequential Logic -Distinguishing States¥ Consider input sequence—X = 0 1 0 1 1 0 0 1 1— Output sequenceZ = 0 0 1 0 1 1 1 1 0— If we change the networkS3->S0 => S3->S3,the output sequencewill be the same¥ Find distinguishing sequence— an input sequence that willdistinguish each state from the otherstatesInput sequence: X=11¥ S0: Z = 01¥ S1: Z = 11¥ S2: Z = 10¥ S3: Z = 007Electrical and Computer EngineeringSpring 2004 Slide #13UAH CPE/EE 422/522Chapter 1010.2 Testing Sequential Logic -Testing Each State TransitionVerify each entry in the table usingthe following sequences:Electrical and Computer EngineeringSpring 2004 Slide #14UAH CPE/EE 422/522Chapter 1010.2 Testing Sequential Logic -Testing Each State Transition (cont’d)¥ Implementation of the FSM— S0=00, S1=10, S2=01, S3=11¥ Test a for s-a-1— to do this Q1Q2 must be 10=> go to the state S1 andthen set X to 0 (R10)— in normal operation,the next state will be S0;if a is s-a-1 then next state isS2— distinguish the state (S0 or S2);apply sequence 11— Final sequence: R1011Normal output: 0101Faulty output: 01108Electrical and Computer EngineeringSpring 2004 Slide #15UAH CPE/EE 422/522Chapter 1010.3 Scan Testing¥ Testing of sequential networks is greatly simplified ifwe can observe the state of _____________ inaddition to observing the network outputs—Connect the output of each flip-flop to one of theIC pins?—Arrange flip-flops to form a ____________ =>shift out the state of flip-flops bit by bit usinga single serial output pin => Scan path testingElectrical and Computer EngineeringSpring 2004 Slide #16UAH CPE/EE 422/522Chapter 1010.3 Scan Path Testing - TransformingFrom Sequential to Combinational¥ Sequential network isseparated into acombinational logicpart and a stateregister composed offlip-flops¥ Two ports FFs(2 D inputs and 2 clock inputs)— D1 is stored in the FF on C1 pulse— D2 is stored in the FF on C2 pulse—Q of each FF is connected to D2 of the next FF