•1CPE/EE 422/522Advanced Logic DesignL08Electrical and Computer EngineeringUniversity of Alabama in Huntsville23/06/2003 UAH-CPE/EE 422/522 AM 2Outline• What we know– How to model Combinational Networks in VHDL• Structural, Dataflow, Behavioral– How to model Flip-flops in VHDL– Processes– Delays (delta, transport, inertial)– How to model FSM in VHDL– Wait statements– Variables, Signals, Arrays• What we do not know– VHDL Operators– Procedures, Functions– Packages, Libraries– Additional Topics (if time)23/06/2003 UAH-CPE/EE 422/522 AM 3Review: Modeling a Sequential MachineMealy Machine for 8421 BCD to 8421 BCD + 3 bit serial converterHow to model this in VHDL?23/06/2003 UAH-CPE/EE 422/522 AM 4Review: Behavioral VHDL ModelTwo processes: • the first represents the combinational network;• the second represents the state register•223/06/2003 UAH-CPE/EE 422/522 AM 5Review: Wait Statements• ... an alternative to a sensitivity list– Note: a process cannot have both wait statement(s)and a sensitivity list• Generic form of a process with wait statement(s)processbeginsequential-statementswait statementsequential-statementswait-statement...end process;How wait statements work?• Execute seq. statement until a wait statement is encountered.• Wait until the specified condition is satisfied.• Then execute the next set of sequential statements until the next wait statement is encountered.• ...• When the end of the process is reached start over again at the beginning.23/06/2003 UAH-CPE/EE 422/522 AM 6Review: Forms of Wait Statements• Wait on – until one of the signals in the sensitivity list changes• Wait for– waits until the time specified by the time expression has elapsed– What is this:wait for 0 ns;• Wait until– the booleanexpression is evaluated whenever one of the signals in the expression changes, and the process continues execution when the expression evaluates to TRUEwait on sensitivity-list;wait for time-expression;wait until boolean-expression;23/06/2003 UAH-CPE/EE 422/522 AM 7Review: Variables• What are they for: Local storage in processes, procedures, and functions• Declaring variablesvariable list_of_variable_names : type_name [ := initial value ];• Variables must be declared within the process in which they are used and are local to the process– Note: exception to this is SHARED variables23/06/2003 UAH-CPE/EE 422/522 AM 8Review: Signals• Signals must be declared outside a process• Declaration formsignal list_of_signal_names : type_name [ := initial value ];• Declared in an architecture can be used anywhere within that architecture•323/06/2003 UAH-CPE/EE 422/522 AM 9Review: Constants• Declaration formconstant constant_name : type_name := constant_value;• Constants declared at the start of an architecturecan be used anywhere within that architecture• Constants declared within a process are localto that processconstant delay1 : time := 5 ns;23/06/2003 UAH-CPE/EE 422/522 AM 10Review: Variables vs. Signals• Variable assignment statementvariable_name := expression;• Signal assignment statementsignal_name <= expression [after delay];– expression is evaluated and the variable is instantaneously updated(no delay, not even delta delay)– expression is evaluated and the signal is scheduled to change after delay; if no delay is specified the signal is scheduled to be updated after a delta delay23/06/2003 UAH-CPE/EE 422/522 AM 11Review: Variables vs. Signals (cont’d)Process Using VariablesProcess Using SignalsSum = ?Sum = ?23/06/2003 UAH-CPE/EE 422/522 AM 12Predefined VHDL Types• Variables, signals, and constants can have any one of the predefined VHDL types or they can have a user-defined type• Predefined Types– bit – {‘0’, ‘1’}– boolean– {TRUE, FALSE}– integer –[-231- 1.. 231– 1}– real – floating point number in range –1.0E38 to +1.0E38– character –legal VHDL characters including lower-uppercase letters, digits, special characters, ...– time – an integer with units fs, ps, ns, us, ms, sec, min, or hr•423/06/2003 UAH-CPE/EE 422/522 AM 13User Defined Type• Common user-defined type is enumeratedtype state_type is (S0, S1, S2, S3, S4, S5); signal state : state_type := S1;• If no initialization, the default initialization is the leftmostelement in the enumeration list (S0 in this example)• VHDL is strongly typed language =>signals and variables of different types cannot be mixed in the same assignment statement,and no automatic type conversion is performed23/06/2003 UAH-CPE/EE 422/522 AM 14Arrays• Exampletype SHORT_WORD is array (15 downto 0) of bit; signal DATA_WORD : SHORT_WORD;variable ALT_WORD : SHORT_WORD := “0101010101010101”;constant ONE_WORD : SHORT_WORD := (others => ‘1’);• ALT_WORD(0) – rightmost bit• ALT_WORD(5 downto 0) – low order 6 bits• General formtype arrayTypeName is array index_range of element_type;signal arrayName : arrayTypeName [:=InitialValues]; 23/06/2003 UAH-CPE/EE 422/522 AM 15Arrays (cont’d)• Multidimensional arraystype matrix4x3 is array (1 to 4, 1 to 3) of integer; variable matrixA: matrix4x3 := ((1,2,3), (4,5,6), (7,8,9), (10,11,12));• matrixA(3, 2) = ?• Unconstrained array typetype intvec is array (natural range<>) of integer; • range must be specified when the array object is declaredsignal intvec5 : intvec(1 to 5) := (3,2,6,8,1);type matrix is array (natural range<>,natural range<>) of integer; 23/06/2003 UAH-CPE/EE 422/522 AM 16Sequential Machine Model Using State Table•523/06/2003 UAH-CPE/EE 422/522 AM 17Predefined Unconstrained Array Types• Bit_vector, stringconstant A : bit_vector(0 to 5) := “10101”;-- (‘1’, ‘0’, ‘1’, ‘0’, ‘1’);• Subtypes subtype SHORT_WORD is : bit_vector(15 to 0);• Predefined subtypes of type integer• POSITIVE (all positive integers)• NATURAL (all positive integers and 0) • include a subset of the values specified by the type23/06/2003 UAH-CPE/EE 422/522 AM 18VHDL Operators1. Binary logical operators: and or nand nor xor xnor2. Relational: = /= < <= > >=3. Shift: sll srl sla sra rol ror4. Adding: + - & (concatenation)5. Unary sign: + -6. Multiplying: * / mod rem7. Miscellaneous: not abs **• Class 7 has the highest precedence (applied first),followed by class 6, then class 5, etc23/06/2003 UAH-CPE/EE 422/522 AM 19Example of VHDL Operators23/06/2003 UAH-CPE/EE 422/522 AM