CPE/EE 422/522 Advanced Logic Design L14Additional Topics in VHDLReview: Operator OverloadingReview: Multivalued LogicReview: Signal ResolutionReview: Signal Resolution (cont’d)Review: Resolution Function for X01ZIEEE 1164 Standard LogicResolution Function for IEEE 9-valuedAND Table for IEEE 9-valuedAND Function for std_logic_vectorsGenericsRise/Fall Time Modeling Using GenericsGenerate Statements4-bit Adder4-bit Adder using GenerateSynthesis of VHDL CodeSynthesis of VHDL Code (cont’d)Unintentional Latch CreationIf StatementsSynthesis of a Case StatementCase Statement: Before and After OptimizationSynthesis of an If StatementStandard VHDL Synthesis PackageNumeric_bit, Numeric_stdNumeric_bit, Numeric_std (cont’d)Slide 27Synthesis Examples (1)Synthesis Examples (2a)Synthesis Examples (2b)Synthesis Examples (2c)FilesSlide 33Standard TEXTIO PackageReading TEXTIO fileExtracting Data from the Line BufferExtracting Data from the Line Buffer (cont’d)Writing to TEXTIO filesAn ExampleAn Example (cont’d)VHDL Code to Fill Memory ArrayVHDL Code to Fill Memory Array (cont’d)Things to RememberThings to Remember (cont’d)Networks for Arithmetic OperationsSlide 46State Graphs for Control NetworksConstraints on Input LabelsConstraints on Input Labels (cont’d)Slide 50Block Diagram of a Binary MultiplierMultiplication ExampleState Graph for Binary MultiplierBehavioral VHDL ModelBehavioral VHDL Model (cont’d)CPE/EE 422/522Advanced Logic DesignL14Electrical and Computer EngineeringUniversity of Alabama in Huntsville01/14/19 UAH-CPE/EE 422/522 AM 2Additional Topics in VHDL•Attributes•Transport and Inertial Delays•Operator Overloading•Multivalued Logic and Signal Resolution•IEEE 1164 Standard Logic•Generics•Generate Statements•Synthesis of VHDL Code•Synthesis Examples•Files and Text IO01/14/19 UAH-CPE/EE 422/522 AM 3Review: Operator Overloading•Operators +, - operate on integers •Write procedures for bit vector addition/subtraction–addvec, subvec•Operator overloading allows using + operator to implicitly call an appropriate addition function•How does it work?–When compiler encounters a function declaration in which the function name is an operator enclosed in double quotes, the compiler treats the function as an operator overloading (“+”)–when a “+” operator is encountered, the compiler automatically checks the types of operands and calls appropriate functions01/14/19 UAH-CPE/EE 422/522 AM 4Review: Multivalued Logic•Bit (0, 1)•Tristate buffers and buses =>high impedance state ‘Z’•Unknown state ‘X’ –e. g., a gate is driven by ‘Z’, output is unknown–a signal is simultaneously driven by ‘0’ and ‘1’01/14/19 UAH-CPE/EE 422/522 AM 5Review: Signal Resolution•VHDL signals may either be resolved or unresolved•Resolved signals have an associated resolution function•Bit type is unresolved – –there is no resolution function–if you drive a bit signal to two different values in two concurrent statements, the compiler will generate an error01/14/19 UAH-CPE/EE 422/522 AM 6Review: Signal Resolution (cont’d)signal R : X01Z := ‘Z’; ...R <= transport ‘0’ after 2 ns, ‘Z’ after 6 ns;R <= transport ‘1’ after 4 ns;R <= transport ‘1’ after 8 ns, ‘0’ after 10 ns;01/14/19 UAH-CPE/EE 422/522 AM 7Review: Resolution Function for X01ZDefine AND and OR for 4-valued inputs?01/14/19 UAH-CPE/EE 422/522 AM 8IEEE 1164 Standard Logic•9-valued logic system–‘U’ – Uninitialized–‘X’ – Forcing Unknown–‘0’ – Forcing 0–‘1’ – Forcing 1–‘Z’ – High impedance–‘W’ – Weak unknown–‘L’ – Weak 0–‘H’ – Weak 1–‘-’ – Don’t careIf forcing and weak signal are tied together, the forcing signal dominates. Useful in modeling the internal operation of certain types of ICs. In this course we use a subset of the IEEE values: X10Z01/14/19 UAH-CPE/EE 422/522 AM 9Resolution Function for IEEE 9-valued01/14/19 UAH-CPE/EE 422/522 AM 10AND Table for IEEE 9-valued01/14/19 UAH-CPE/EE 422/522 AM 11AND Function for std_logic_vectors01/14/19 UAH-CPE/EE 422/522 AM 12Generics•Used to specify parameters for a component in such a way that the parameter values must be specified when the component is instantiated •Example: rise/fall time modeling01/14/19 UAH-CPE/EE 422/522 AM 13Rise/Fall Time Modeling Using Generics01/14/19 UAH-CPE/EE 422/522 AM 14Generate Statements•Provides an easy way of instantiating components when we have an iterative array of identical components•Example: 4-bit RCA01/14/19 UAH-CPE/EE 422/522 AM 154-bit Adder01/14/19 UAH-CPE/EE 422/522 AM 164-bit Adder using Generate01/14/19 UAH-CPE/EE 422/522 AM 17Synthesis of VHDL Code•Synthesizer–take a VHDL code as an input–synthesize the logic: output may be a logic schematic with an associated wirelist•Synthesizers accept a subset of VHDL as input•Efficient implementation?•ContextA <= B and C;...wait until clk’event and clk = ‘1’;A <= B and C;Implies CM for AImplies a register or flip-flop01/14/19 UAH-CPE/EE 422/522 AM 18Synthesis of VHDL Code (cont’d)•When use integers specify the range–if not specified, the synthesizer may infer 32-bit register•When integer range is specified,most synthesizers will implement integer addition and subtraction using binary adders with appropriate number of bits•General rule: when a signal is assigned a value,it will hold that value until it is assigned new value01/14/19 UAH-CPE/EE 422/522 AM 19Unintentional Latch CreationWhat if a = 3?The previous value of b should be held in the latch, so G should be 0 when a = 3.To eliminate latch => replace the word null with b <= 0;01/14/19 UAH-CPE/EE 422/522 AM 20If Statementsif A = ‘1’ then NextState <= 3;end if;What if A /= 1?Retain the previous value for NextState?Synthesizer might interpret this to mean that NextState is unknown!if A = ‘1’ then NextState <= 3;else NextState <= 2;end if;01/14/19 UAH-CPE/EE 422/522 AM 21Synthesis of a Case Statement01/14/19 UAH-CPE/EE 422/522 AM 22Case Statement: Before and After Optimization01/14/19 UAH-CPE/EE 422/522 AM 23Synthesis of an If StatementSynthesized code before optimization01/14/19 UAH-CPE/EE 422/522 AM 24Standard VHDL Synthesis Package•Every VHDL synthesis tool provides its own package of functions for operations commonly used in hardware models•IEEE is developing a standard synthesis