Outline What we know Combinational Networks Sequential Networks CPE EE 422 522 Advanced Logic Design L05 Basic Building Blocks Mealy Moore Machines Max Frequency Setup Hold Times Synchronous Design What we do not know Electrical and Computer Engineering University of Alabama in Huntsville Equivalent states and reduction of state tables Hardware Description Languages UAH CPE EE 422 522 AM 11 06 2003 2 Review General Model of Moore Sequential Machine Review Mealy Sequential Networks Outputs depend only on present state General model of Mealy Sequential Network Combinational Network Next State Inputs X Combinational Network State Register Outputs Z State Q Clock 1 X inputs are changed to a new value 2 After a delay the Z outputs and next state appear at the output of CM 3 The next state is clocked into the state register and the state changes 11 06 2003 UAH CPE EE 422 522 AM 3 X x1 x 2 xn Q Q 1 Q 2 Q k Z z1 z2 zm 11 06 2003 Intro to VHDL 4 Developed originally by DARPA 1 billion transistor chip running at 20 GHz in 2007 for specifying digital systems Need for Hardware Description Languages International IEEE standard IEEE 1076 1993 Hardware Description Simulation Synthesis Provides a mechanism for digital design and reusable design documentation Support different description levels Systems become more complex Design at the gate and flip flop level becomes very tedious and time consuming HDLs allow Design and debugging at a higher level before conversion to the gate and flip flop level Tools for synthesis do the conversion Structural specifying interconnections of the gates Dataflow specifying logic equations and VHDL Verilog VHDL VHSIC Hardware Description Language UAH CPE EE 422 522 AM UAH CPE EE 422 522 AM Intro to VHDL Technology trends 11 06 2003 Q t G X t Q t Z t F Q t Behavioral specifying behavior Top down Technology Dependent 5 11 06 2003 UAH CPE EE 422 522 AM 6 1 VHDL Description of Combinational Networks Entity Architecture Pair Full Adder Example 11 06 2003 UAH CPE EE 422 522 AM 7 11 06 2003 VHDL Program Structure 11 06 2003 UAH CPE EE 422 522 AM UAH CPE EE 422 522 AM 8 4 bit Adder 9 11 06 2003 4 bit Adder cont d 11 06 2003 UAH CPE EE 422 522 AM UAH CPE EE 422 522 AM 10 4 bit Adder Simulation 11 11 06 2003 UAH CPE EE 422 522 AM 12 2 Modeling Flip Flops Using VHDL Processes Concurrent Statements vs Process A B C D are integers A 1 B 2 C 3 D 0 D changes to 4 at time 10 General form of process Whenever one of the signals in the sensitivity list changes the sequential statements are executed in sequence one time 11 06 2003 UAH CPE EE 422 522 AM Simulation Results time delta A B C 0 0 0 1 2 10 0 1 2 3 10 1 1 2 4 10 2 1 4 4 10 3 4 4 4 13 11 06 2003 D Flip flop Model D 0 4 4 4 4 stat 3 exe stat 2 exe stat 1 exe no exec UAH CPE EE 422 522 AM 14 JK Flip Flop Model Bit values are enclosed in single quotes 11 06 2003 UAH CPE EE 422 522 AM 15 11 06 2003 JK Flip Flop Model 11 06 2003 UAH CPE EE 422 522 AM UAH CPE EE 422 522 AM 16 Using Nested IFs and ELSEIFs 17 11 06 2003 UAH CPE EE 422 522 AM 18 3 VHDL Models for a MUX MUX Models 1 library IEEE use IEEE std logic 1164 all use IEEE std logic unsigned all entity SELECTOR is port A in std logic vector 15 downto 0 SEL in std logic vector 3 downto 0 Sel represents the integer equivalent of a 2 bit binary number with bits A and B Y out std logic end SELECTOR If a MUX model is used inside a process the MUX can be modeled using a CASE statement cannot use a concurrent statement 11 06 2003 UAH CPE EE 422 522 AM 19 11 06 2003 MUX Models 2 architecture RTL3 of SELECTOR is library IEEE use IEEE std logic 1164 all begin use IEEE std logic 1164 all with SEL select Y A 0 when 0000 port use IEEE std logic unsigned all entity SELECTOR is A 1 when 0001 A in std logic vector 15 downto 0 A 2 when 0010 SEL in std logic vector 3 downto 0 A 3 when 0011 Y out std logic A 4 when 0100 end SELECTOR port A in std logic vector 15 downto 0 SEL in std logic vector 3 downto 0 Y out std logic A 5 when 0101 end SELECTOR A 6 when 0110 A 7 when 0111 A 8 when 1000 A 9 when 1001 A 10 when 1010 A 11 when 1011 A 12 when 1100 A 13 when 1101 A 14 when 1110 A 15 when others end RTL3 11 06 2003 UAH CPE EE 422 522 AM 21 MUX Models 4 library IEEE architecture RTL4 of SELECTOR is use IEEE std logic 1164 all begin use IEEE std logic unsigned all entity SELECTOR is Y A conv integer SEL end RTL4 20 11 06 2003 architecture RTL2 of SELECTOR is begin p1 process A SEL begin case SEL is when 0000 Y A 0 when 0001 Y A 1 when 0010 Y A 2 when 0011 Y A 3 when 0100 Y A 4 when 0101 Y A 5 when 0110 Y A 6 when 0111 Y A 7 when 1000 Y A 8 when 1001 Y A 9 when 1010 Y A 10 when 1011 Y A 11 when 1100 Y A 12 when 1101 Y A 13 when 1110 Y A 14 when others Y A 15 end case end process endRTL2 UAH CPE EE 422 522 AM 22 Compilation and Simulation of VHDL Code Compiler Analyzer checks the VHDL source code does it conforms with VHDL syntax and semantic rules are references to libraries correct port Intermediate form used by a simulator or by a synthesizer Elaboration A in std logic vector 15 downto 0 SEL in std logic vector 3 downto 0 Y out std logic create ports allocate memory storage create interconnections establish mechanism for executing of VHDL processes end SELECTOR 11 06 2003 UAH CPE EE 422 522 AM MUX Models 3 library IEEE use IEEE std logic unsigned all entity SELECTOR is architecture RTL1 of SELECTOR is begin p0 process A SEL begin if SEL 0000 then Y A 0 elsif SEL 0001 then Y A 1 elsif SEL 0010 then Y A 2 elsif SEL 0011 then Y A 3 elsif SEL 0100 then Y A 4 elsif SEL 0101 then Y A 5 elsif SEL 0110 then Y A 6 elsif SEL 0111 then Y A 7 elsif SEL 1000 then Y A 8 elsif SEL 1001 then Y A 9 elsif SEL 1010 then Y A 10 elsif SEL 1011 then Y A 11 …