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•1CPE/EE 422/522Advanced Logic DesignL04Electrical and Computer EngineeringUniversity of Alabama in Huntsville09/06/2003 UAH-CPE/EE 422/522 AM 2Outline• What we know– Combinational Networks• Analysis, Synthesis, Simplification,Hazards, Building Blocks, PALs, PLAs, ROMs– Sequential Networks: Basic Building Blocks– Design: Mealy– Setup and hold times, Max clock frequency• What we do not know– Design: Moore– Equivalent States– State Table Reduction– Intro to VHDL09/06/2003 UAH-CPE/EE 422/522 AM 3Review: Mealy Sequential NetworksGeneral model of Mealy Sequential Network(1) X inputs are changed to a new value(2) After a delay, the Z outputs and next state appear at the output of CM(3) The next state is clocked into the state register and the state changes09/06/2003 UAH-CPE/EE 422/522 AM 4Review: 8421 BCD to Excess3 BCD Code ConverterxzQ00111001110100010101111010010110000110101110001001101100101001000010100011000000t0t1t2t3t0t1t2t3Z (outputs)X (inputs)09/06/2003 UAH-CPE/EE 422/522 AM 5Sequential Network Timing (cont’d)Timing diagram assuming a propagation delay of 10 ns for each flip-flop and gate(State has been replaced with the state of three flip-flops)09/06/2003 UAH-CPE/EE 422/522 AM 6Setup and Hold Times• For a real D-FF – D input must be stable for a certain amount of time before the active edge of clock cycle => Setup time– D input must be stable for a certain amount of timeafter the active edge of the clock => Hold time• Propagation time: from the time the clock changes to the time the output changesManufacturers provide minimum tsu, th, and maximum tplh, tphl•209/06/2003 UAH-CPE/EE 422/522 AM 7Maximum Clock Frequencymaxct - Max propagation delay through the combinational networkmaxpt- Max propagation delay from the time the clock changes to the flip-flop output changes { = max(tplh, tphl)}ckt- Clock periodsuckmaxpmaxctttt −≤+sumaxpmaxccktttt ++≥Example:MHznsfns*tnst,nst,nstmaxckgatesumaxp205015051515215515===++====09/06/2003 UAH-CPE/EE 422/522 AM 8Hold Time Violation• Occur if the change in Q fed back through the combinational network and cause D to change too soon after the clock edgehmincminpttt ≥+Hold time is satisfied if:What about X?sumaxcxxttt +≥Make sure that input changes propagate to the flip-flops inputs such that setup time is satisfied.Make sure that X does not change too soon after the clock. If X changes at time ty after the active edge, hold time is satisfied ifmincxhyttt −≥09/06/2003 UAH-CPE/EE 422/522 AM 9Moore Sequential NetworksOutputs depend only on present state!))t(Q(F)t(Z =x1x2xnz1z2zmZ = z1z2... zmX = x1x2... xnQ = Q1Q2... Qk))t(Q),t(X(G)t(Q =+Q09/06/2003 UAH-CPE/EE 422/522 AM 10General Model of Moore Sequential Machine))t(Q(F)t(Z =Inputs(X)ClockZ = z1z2... zmX = x1x2... xnQ = Q1Q2... Qk))t(Q),t(X(G)t(Q =+Combinational NetworkState RegisterNext StateOutputs depend only on present state!Outputs(Z)State(Q)Combinational Network09/06/2003 UAH-CPE/EE 422/522 AM 11Code Converter: Moore MachineS00S11S20S31S40S51S80S71S60S90S1010NC C10NC1C C01NCNCCNCNCStart01100101010101009/06/2003 UAH-CPE/EE 422/522 AM 12Code Converter: Moore MachineS00S11S20S31S40S51S80S71S60S90S1010NC C10NC1C C0 1NCNCCNCNCStart01100 1 010101010Do we need state S0?How many states does Moore machine have?How many states does Mealy machine have?•309/06/2003 UAH-CPE/EE 422/522 AM 13Moore Machine: State TableS00S11S20S31S40S51S80S71S60S90S1010NCC10NC1C C01NCNCCNCNCStart01100 1 0101010101S2S1S100S2S1S90-S10S81S10S9S70S10S9S61S8S7S50S8S7S41S7S6S30S5S4S21S4S3S10S2S1S0X=1X=0ZNS PSNote: state S0 could be eliminated (S0 == S9), if S9 was start state!09/06/2003 UAH-CPE/EE 422/522 AM 14Moore Machine Timing• X = 0010_1001 => Z = 1110_0011MooreMealy09/06/2003 UAH-CPE/EE 422/522 AM 15State AssignmentsGuidelines to reduce the amount of combinational logic1S2S1S100S2S1S90-S10S81S10S9S70S10S9S61S8S7S50S8S7S41S7S6S30S5S4S21S4S3S10S2S1S0X=1X=0ZNS PSRule I: (S0, S9, S10), (S4, S5), (S6, S7)Rule II: (S1, S2), (S3, S4), (S4, S5), (S6, S7), (S7, S8), (S9, S10)Rule III: (S0, S2, S4, S6, S8, S9)(S1, S3, S5, S7, S10)S9 s10 S8 S5 S1 S3 S4 S0 S2 S7 S600 01 11 1000011110Q1Q2Q3Q4S0 – 0010S1 - 0111….S10 - 010009/06/2003 UAH-CPE/EE 422/522 AM 16Moore Machine: Another Example• Coding schemes for serial data transmission– NRZ: nonreturn-to-zero– NRZI: nonreturn-to-zero-inverted• 0 in input sequence – the bit transmitted is the same as the previous bit; • 1 in input sequence – transmit the complement of the previous bit– RZ: return-to-zero• 0 – 0 for full bit time; 1 – 1 for the first half, 0 for the second half– ManchesterA Converter for Serial Data Transmission: NRZ-to-Manchester09/06/2003 UAH-CPE/EE 422/522 AM 17Moore Network for NRZ-to-Manchester09/06/2003 UAH-CPE/EE 422/522 AM 18Moore Network for NRZ-to-Manchester•409/06/2003 UAH-CPE/EE 422/522 AM 19Synchronous Design• Use a clock to synchronize the operation of all flip-flops, registers, and counters in the system– all changes occur immediately following the active clock edge– clock period must be long enough so that all changes flip-flops, registers, counters will have time to stabilize before the next active clock edge• Typical design: Control section + Data SectionData registersArithmetic UnitsCountersBuses, Muxes, …Sequential machineto generate control signals to control the operation of data section09/06/2003 UAH-CPE/EE 422/522 AM 20An Example• Data section // s= n*(n+a) // R1=n, R2=a // R1=s• Design flowchart for SMUL operation• Design Control section• S0 S1 F0 0 B0 1 B – C01 0 B + C01 1 A + BR2rdld LD(R2)RD(R2)16L1clldLD(L1)CL(L1)161616ALUS0S1C0LD(A) RD(A)1616ACL(A)ld rdclFA B16R1rdldLD(R1)RD(R1)BRLD(BR)F15..0DEC(BR)RD(BR)16rdlddec+BR016C1609/06/2003 UAH-CPE/EE 422/522 AM 21Timing Chart for System with Falling-edge Devices09/06/2003 UAH-CPE/EE 422/522 AM 22Timing Chart for System with Rising-edge Devices09/06/2003 UAH-CPE/EE 422/522 AM 23Principles of Synchronous Design• Method– All clock inputs to flip-flops, registers, counters, etc.,are driven directly from the system clock or from the clock ANDed with a control signal• Result– All state changes occur immediately following the active edge of the clock signal• Advantage– All switching transients, switching noise, etc., occur between the clock pulses and have no effect on system


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