UAH CPE 422 - Advanced Logic Design (13 pages)

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Advanced Logic Design



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Outline VHDL What we know additional topics CPE EE 422 522 Advanced Logic Design L15 Electrical and Computer Engineering University of Alabama in Huntsville Attributes Transport and Inertial Delays Operator Overloading Multivalued Logic and Signal Resolution IEEE 1164 Standard Logic Generics Generate Statements Synthesis of VHDL Code Synthesis Examples What we don t know Files and Text IO Networks for Arithmetic Operations SM Charts 16 07 2003 Files UAH CPE EE 422 522 AM 2 Files File input output in VHDL Used in test benches Source of test data Storage for test results VHDL provides a standard TEXTIO package read write lines of text 16 07 2003 UAH CPE EE 422 522 AM 3 16 07 2003 UAH CPE EE 422 522 AM 4 1 Standard TEXTIO Package Reading TEXTIO file Readline reads a line of text and places it in a buffer with an associated pointer Pointer to the buffer must be of type line which is declared in the textio package as Contains declarations and procedures for working with files composed of lines of text Defines a file type named text type text is file of string Contains procedures for reading lines of text from a file of type text and for writing lines of text to a file type line is access string When a variable of type line is declared it creates a pointer to a string Code variable buff line readline test data buff reads a line of text from test data and places it in a buffer which is pointed to by buff 16 07 2003 UAH CPE EE 422 522 AM 5 Extracting Data from the Line Buffer 6 TEXTIO provides overloaded read procedures to read data of types bit bit vector boolean character integer real string and time from buffer Read forms read buff bv4 extracts a 4 bit vector from the buffer sets bv4 equal to this vector and adjusts the pointer buff to point to the next character in the buffer Another call to read will then extract the next data object from the line buffer UAH CPE EE 422 522 AM UAH CPE EE 422 522 AM Extracting Data from the Line Buffer cont d To extract data from the line buffer call a read procedure one or more times For example if bv4 is a bit vector of length four the call 16 07 2003 16 07 2003 7 read pointer value read pointer value good good is boolean that returns TRUE if the read is successful and FALSE if it is not type and size of value determines which of the read procedures is called character strings and bit vectors within files of type text are not delimited by quotes 16 07 2003 UAH CPE EE 422 522 AM 8 2 Writing to TEXTIO files An Example Call one or more write procedures to write data to a line buffer and then call writeline to write the line to a file Procedure to read data from a file and store the data in a memory array Format of the data in the file variable buffw line address N comments byte1 byte2 byteN comments variable int1 integer variable bv8 bit vector 7 downto 0 write buffw int1 right 6 right just 6 ch wide write buffw bv8 right 10 writeln buffw output file Write parameters 1 buffer pointer of type line 2 a value of any acceptable type 3 justification left or right and 4 field width number of characters 16 07 2003 UAH CPE EE 422 522 AM 9 16 07 2003 An Example cont d address 4 hex digits N indicates the number of bytes of code bytei 2 hex digits each byte is separated by one space the last byte must be followed by a space anything following the last state will not be read and will be treated as a comment UAH CPE EE 422 522 AM 10 VHDL Code to Fill Memory Array Code sequence an example 12AC 7 7 hex bytes follow AE 03 B6 91 C7 00 0C LDX imm LDA dir STA ext 005B 2 2 bytes follow 01 FC TEXTIO does not include read procedure for hex numbers we will read each hex value as a string of characters and then convert the string to an integer How to implement conversion table lookup constant named lookup is an array of integers indexed by characters in the range 0 to F this range includes the 23 ASCII characters 0 1 9 A F corresponding values 0 1 9 1 1 1 1 1 1 1 10 11 12 13 14 15 16 07 2003 UAH CPE EE 422 522 AM 11 16 07 2003 UAH CPE EE 422 522 AM 12 3 VHDL Code to Fill Memory Array cont d Things to Remember Attributes associated to signals allow checking for setup hold times and other timing specifications Attributes associated to arrays allow us to write procedures that do not depend on the manner in which arrays are indexed Inertial and transport delays allow modeling of different delay types that occur in real systems Operator overloading allow us to extend the definition of VHDL operators so that they can be used with different types of operands UAH CPE EE 422 522 AM 16 07 2003 13 Things to Remember cont d 16 07 2003 UAH CPE EE 422 522 AM 14 Networks for Arithmetic Operations Multivalued logic and the associated resolution functions Case Study Serial Adder with Accumulator allow us to model tri state buses and systems where a signal is driven by more than one source Generics allow us to specify parameter values for a component when the component is instantiated Generate statements efficient way to describe systems with iterative structure TEXTIO convenient way for file input output 16 07 2003 UAH CPE EE 422 522 AM 15 16 07 2003 UAH CPE EE 422 522 AM 16 4 Networks for Arithmetic Operations State Graphs for Control Networks Serial Adder with Accumulator Use variable names instead of 0s and 1s E g XiXj ZpZq if Xi and Xj inputs are 1 the outputs Zp and Zq are 1 all other outputs are 0s E g X X1X2X3X4 Z Z1Z2Z3Z4 X1X4 Z2Z3 1 0 0 1 1 0 16 07 2003 UAH CPE EE 422 522 AM 17 Constraints on Input Labels 16 07 2003 UAH CPE EE 422 522 AM 18 Constraints on Input Labels cont d Assume I input expression we traverse the arc when I 1 Assures that at most one input label can be 1 at any given time Assures that at least one input label will be 1 at any given time 1 2 Exactly one label will be 1 the next state will be uniquely defined for every input combination 16 07 2003 UAH CPE EE 422 522 AM 19 16 07 2003 UAH CPE EE 422 522 AM 20 5 Networks for Arithmetic Operations Block Diagram of a Binary Multiplier Case Study Serial Parallel Multiplier Note we use unsigned binary numbers Ad add signal adder outputs are stored into the ACC Sh shift signal shift all 9 bits to right Ld load signal load …


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