11Electrical and Computer EngineeringCPE/EE 422/522 Chapter 2 –Introduction to VHDLDr. Rhonda Kay GaedeUAHElectrical and Computer EngineeringPage 2 of 78 UAH CPE/EE 422/522Chapter 2Motivation for VHDL• Technology trends– 1 billion transistor chip running at 20 GHz in 2007• Need for Hardware Description Languages– Systems become more complex– Design at the gate and flip-flop level becomes very tedious and time consuming• HDLs allow– Design and debugging at a higher level before conversion to the gate and flip-flop level– Tools for synthesis do the conversion•VHDL, Verilog• VHDL – VHSIC Hardware Description Language2Electrical and Computer EngineeringPage 3 of 78 UAH CPE/EE 422/522Chapter 2Facts About VHDL• Developed originally by DARPA– for specifying digital systems• International IEEE standard (IEEE 1076-1993)• Hardware Description, Simulation, Synthesis• Provides a mechanism for digital design and reusable design documentation• Support different description levels– Structural (specifying interconnections of the gates), – Dataflow (specifying logic equations), and – Behavioral (specifying behavior)• Top-down, Technology IndependentElectrical and Computer EngineeringPage 4 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks – The Basics3Electrical and Computer EngineeringPage 5 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks – Entity Architecture PairFull Adder ExampleElectrical and Computer EngineeringPage 6 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks – Hierarchy of VHDL Models4Electrical and Computer EngineeringPage 7 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks – Adder4FA3FA2FA1FA0Electrical and Computer EngineeringPage 8 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks - Structural Adder45Electrical and Computer EngineeringPage 9 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks - Providing StimuliElectrical and Computer EngineeringPage 10 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks – Testbench6Electrical and Computer EngineeringPage 11 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks - Altera Full Adder SimulationElectrical and Computer EngineeringPage 12 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks - Altera Adder4 Simulation7Electrical and Computer EngineeringPage 13 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks - Behavioral Adder4Electrical and Computer EngineeringPage 14 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks - Behavioral Adder48Electrical and Computer EngineeringPage 15 of 78 UAH CPE/EE 422/522Chapter 22.1 VHDL Description of Combinational Networks - Behavioral Adder4 SimulationElectrical and Computer EngineeringPage 16 of 78 UAH CPE/EE 422/522Chapter 2• Whenever one of the signals in the sensitivity list changes, thesequential statements are executed in sequence one timeGeneral form of process2.2 Modeling Flip-Flops Using VHDL Processes - The Process Statement9Electrical and Computer EngineeringPage 17 of 78 UAH CPE/EE 422/522Chapter 2A, B, C, D are integers A=1, B=2, C=3, D=0 D changes to 4 at time 10time delta A B C D2.2 Modeling Flip-Flops Using VHDL Processes - Sequential Statementstime delta A B C DElectrical and Computer EngineeringPage 18 of 78 UAH CPE/EE 422/522Chapter 22.2 Modeling Flip-Flops Using VHDL Processes - Modeling a D Flip-Flop10Electrical and Computer EngineeringPage 19 of 78 UAH CPE/EE 422/522Chapter 22.2 Modeling Flip-Flops Using VHDL Processes - Modeling a D LatchElectrical and Computer EngineeringPage 20 of 78 UAH CPE/EE 422/522Chapter 22.2 Modeling Flip-Flops Using VHDL Processes - D Flip-Flop versus D Latch11Electrical and Computer EngineeringPage 21 of 78 UAH CPE/EE 422/522Chapter 22.2 Modeling Flip-Flops Using VHDL Processes - Altera DFF SimulationElectrical and Computer EngineeringPage 22 of 78 UAH CPE/EE 422/522Chapter 22.2 Modeling Flip-Flops Using VHDL Processes - Altera D Latch Simulation12Electrical and Computer EngineeringPage 23 of 78 UAH CPE/EE 422/522Chapter 2Building a Shift Register with D Flip-flop Building BlocksElectrical and Computer EngineeringPage 24 of 78 UAH CPE/EE 422/522Chapter 2Building a Shift Register with D Flip-flop Building Blocks13Electrical and Computer EngineeringPage 25 of 78 UAH CPE/EE 422/522Chapter 2Testing the Shift RegisterElectrical and Computer EngineeringPage 26 of 78 UAH CPE/EE 422/522Chapter 2A Behavioral Shift Register Model14Electrical and Computer EngineeringPage 27 of 78 UAH CPE/EE 422/522Chapter 2Another Behavioral Shift Register ModelElectrical and Computer EngineeringPage 28 of 78 UAH CPE/EE 422/522Chapter 2Shift Register Simulation Results15Electrical and Computer EngineeringPage 29 of 78 UAH CPE/EE 422/522Chapter 22.2 Modeling Flip-Flops Using VHDL Processes - Modeling a JK Flip-FlopElectrical and Computer EngineeringPage 30 of 78 UAH CPE/EE 422/522Chapter 22.2 Modeling Flip-Flops Using VHDL Processes - Nested If-then-else16Electrical and Computer EngineeringPage 31 of 78 UAH CPE/EE 422/522Chapter 22.3 VHDL Models for a MultiplexerElectrical and Computer EngineeringPage 32 of 78 UAH CPE/EE 422/522Chapter 2library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR isport (A :in std_logic_vector(15 downto 0);SEL:in std_logic_vector( 3 downto 0);Y :out std_logic);end SELECTOR;architecture RTL1 of SELECTOR isbeginp0 : process (A, SEL)beginif (SEL = "0000") then Y <= A(0);elsif (SEL = "0001") then Y <= A(1);elsif (SEL = "0010") then Y <= A(2);elsif (SEL = "0011") then Y <= A(3);elsif (SEL = "0100") then Y <= A(4);elsif (SEL = "0101") then Y <= A(5);elsif (SEL = "0110") then Y <= A(6);elsif (SEL = "0111") then Y <= A(7);elsif (SEL = "1000") then Y <= A(8);elsif (SEL = "1001") then Y <= A(9);elsif (SEL = "1010") then Y <= A(10);elsif (SEL = "1011") then Y <= A(11);elsif (SEL = "1100") then Y <= A(12);elsif (SEL = "1101") then Y <= A(13);elsif (SEL = "1110") then Y <= A(14);else Y <= A(15);end if;end process;end RTL1;2.3 VHDL Models for a Multiplexer -If Statements17Electrical and Computer EngineeringPage 33 of 78 UAH CPE/EE 422/522Chapter 2library