CPE/EE 422/522 Advanced Logic Design L17Networks for Arithmetic OperationsBlock Diagram of a Binary MultiplierMultiplication ExampleState Graph for Binary MultiplierBehavioral VHDL ModelBehavioral VHDL Model (cont’d)Multiplier Control with CounterMultiplier Control with Counter (cont’d)Slide 10Operation of a Multiplier Using CounterArray MultiplierArray Multiplier (cont’d)Slide 14Multiplication of Signed Binary NumbersSlide 162’s Complement MultiplierState Graph for 2’s Complement MultiplierFaster MultiplierState Graph for Faster MultiplierBehavioral Model for Faster MultiplierSlide 22Command File and SimulationTest Bench for Signed MultiplierHardware Testing and Design for TestabilityTesting Combinational LogicStuck-at FaultsStuck-at Faults for AND and OR gatesTesting an AND-OR NetworkPath Detection & Sensitization: Small ExampleAn ExampleAn Example (cont’d)Testing Sequential LogicTesting Sequential Logic (cont’d)Slide 35Slide 36Slide 37Scan TestingScan Path TestingSlide 40Scan Path Testing: An ExampleScan ChainScan Test with Multiple ICsBoundary ScanBoundary Scan RegisterPCB with Boundary Scan ICsBoundary Scan CellBasic Boundary Scan ArchitectureTAP ControllerTAP Controller: How it Works (I)Instructions in the IEEE StandardInterconnection Testing using Boundary ScanSteps Required to Test ConnectionsSteps Required to Test Connections (cont’d)Slide 55Slide 56Slide 57Built-In Self-TestSelf-Test Circuit for RAMLinear Feedback Shift Registers (LFSR)Self-Test Circuit for RAM with Signature RegsCPE/EE 422/522Advanced Logic DesignL17Electrical and Computer EngineeringUniversity of Alabama in Huntsville01/13/19 UAH-CPE/EE 422/522 AM 2Networks for Arithmetic OperationsCase Study: Serial Parallel MultiplierNote: we use unsigned binary numbers01/13/19 UAH-CPE/EE 422/522 AM 3Block Diagram of a Binary MultiplierAd – add signal // adder outputs are stored into the ACCSh – shift signal // shift all 9 bits to rightLd – load signal // load multiplier into the 4 lower bits of the ACC and clear the upper 5 bits01/13/19 UAH-CPE/EE 422/522 AM 4Multiplication Example01/13/19 UAH-CPE/EE 422/522 AM 5State Graph for Binary Multiplier01/13/19 UAH-CPE/EE 422/522 AM 6Behavioral VHDL Model01/13/19 UAH-CPE/EE 422/522 AM 7Behavioral VHDL Model (cont’d)01/13/19 UAH-CPE/EE 422/522 AM 8Multiplier Control with Counter•Current design: control part generates the control signals (shift/add) and counts the number of steps•If the number of bits is large (e.g., 64),the control network can be divided intoa counter and a shift/add control01/13/19 UAH-CPE/EE 422/522 AM 9Multiplier Control with Counter (cont’d)Add-shifts control: tests St and M and generates the proper sequence of add and shift signalsCounter control: counter generates a completion signal K that stops the multiplier after the proper number of shiftshave been completed01/13/19 UAH-CPE/EE 422/522 AM 10Multiplier Control with Counter (cont’d)• Increment counter each time a shift signal is generated• Generate K after n-1 shifts occured01/13/19 UAH-CPE/EE 422/522 AM 11Operation of a Multiplier Using Counter01/13/19 UAH-CPE/EE 422/522 AM 12Array Multiplier• What do we need to realize Array Multiplier?• AND gates = ?• FA = ?• HA = ?01/13/19 UAH-CPE/EE 422/522 AM 13Array Multiplier (cont’d)01/13/19 UAH-CPE/EE 422/522 AM 14Array Multiplier (cont’d)•Complexity of the N-bit array multiplier–number of AND gates = ?–number of HA = ?–number of FA = ?•Delay–tg – longest AND gate delay–tad – longest possible delay through an adder01/13/19 UAH-CPE/EE 422/522 AM 15Multiplication of Signed Binary Numbers•How to multiply signed binary numbers?•Procedure–Complement the multiplier if negative–Complement the multiplicand if negative–Multiply two positive binary numbers–Complement the product if it should be negative•Simple but requires more hardware and timethan other available methods01/13/19 UAH-CPE/EE 422/522 AM 16Multiplication of Signed Binary Numbers•Four cases–Multiplicand is positive, multiplier is positive–Multiplicand is negative, multiplier is positive–Multiplicand is positive, multiplier is negative–Multiplier is negative, multiplicand is negative•Examples–0111 x 0101 = ?–1101 x 0101 = ?–0101 x 1101 = ?–1011 x 1101 = ?•Preserve the sign of the partial product at each step•If multiplier is negative, complement the multiplicand before adding it in at the last step01/13/19 UAH-CPE/EE 422/522 AM 172’s Complement Multiplier01/13/19 UAH-CPE/EE 422/522 AM 18State Graph for 2’s Complement Multiplier01/13/19 UAH-CPE/EE 422/522 AM 19Faster Multiplier •Move wires from the adder outputs one position to the right =>add and shift can occur at the same clock cycle01/13/19 UAH-CPE/EE 422/522 AM 20State Graph for Faster Multiplier01/13/19 UAH-CPE/EE 422/522 AM 21Behavioral Model for Faster Multiplier01/13/19 UAH-CPE/EE 422/522 AM 22Behavioral Model for Faster Multiplier01/13/19 UAH-CPE/EE 422/522 AM 23Command File and Simulation01/13/19 UAH-CPE/EE 422/522 AM 24Test Bench for Signed Multiplier01/13/19 UAH-CPE/EE 422/522 AM 25Hardware Testing and Design for Testability•Testing during design process–use VHDL test benches to verify that the overall design and algorithms used are correct–verify timing and logic after the synthesis•Post-fabrication testing–when a digital system is manufactured,test to verify that it is free from manufacturing defects–today, cost of testing is major component of the manufacturing cost–efficient techniques are needed to test anddesign digital systems so that they are easy to test01/13/19 UAH-CPE/EE 422/522 AM 26Testing Combinational Logic•Common types of errors–short circuit–open circuit•If the input to a gate is shorted to ground,the input acts as if it is stuck at logic 0–s-a-0 (stuck-at-0) faults•If the input to a gate is shorted to positive supply voltage, the input acts as if it is stuck at logic 1–s-a-1 (stuck-at-1) faults01/13/19 UAH-CPE/EE 422/522 AM 27Stuck-at Faults•How many single stuck-at faults —–2 (n + 1) — where n is the number of inputs•We will assume –that there is only one stuck-at-fault active at a time in the whole circuit–“SSF” — single stuck-at faults-a-0s-a-0s-a-0s-a-1s-a-1s-a-101/13/19 UAH-CPE/EE 422/522 AM 28Stuck-at Faults for AND and OR gatesTest a for s-a-0Test a for s-a-1Test a for s-a-1Test