CPE/EE 422/522 Advanced Logic Design L03OutlineSequential NetworksReview: Clocked D Flip-Flop with Rising-edge TriggerReview: Clocked JK Flip-FlopReview: Clocked T Flip-FlopReview: S-R Latch, Transparent D-LatchMealy Sequential NetworksAn Example: 8421 BCD to Excess3 BCD Code ConverterState Graph and Table for Code ConverterState Assignment RulesTransition TableK-mapsRealizationSequential Network TimingSequential Network Timing (cont’d)Setup and Hold TimesMaximum Clock FrequencyHold Time ViolationMoore Sequential NetworksGeneral Model of Moore Sequential MachineCode Converter: Moore MachineSlide 23Moore Machine: State TableMoore Machine TimingState AssignmentsMoore Machine: Another ExampleMoore Network for NRZ-to-ManchesterSlide 29Synchronous DesignAn ExampleTiming Chart for System with Falling-edge DevicesTiming Chart for System with Rising-edge DevicesPrinciples of Synchronous DesignAsynchronous DesignTo DoCPE/EE 422/522Advanced Logic DesignL03Electrical and Computer EngineeringUniversity of Alabama in Huntsville01/14/19 UAH-CPE/EE 422/522 AM 2Outline•What we know–Combinational Networks•Analysis, Synthesis, Simplification,Building Blocks, PALs, PLAs, ROMs–Sequential Networks: Basic Building Blocks•What we do not know–Design: Mealy, Moore–Sequential Network Timing–Setup and hold times–Max clock frequency01/14/19 UAH-CPE/EE 422/522 AM 3Sequential Networks•Have memory (state)–Present state depends not only on the current input, but also on all previous inputs (history)–Future state depends on the current input and state))t(Q),t(X(F)t(Z x1x2xnz1z2zmZ = z1 z2... zmX = x1 x2... xnQ = Q1 Q2... Qk))t(Q),t(X(G)t(Q QFlip-flops are commonly used as storage devices:D-FF, JK-FF, T-FF01/14/19 UAH-CPE/EE 422/522 AM 4Review: Clocked D Flip-Flop with Rising-edge TriggerNext stateThe next state in response to the rising edge of the clock is equal to the D input before the rising edge01/14/19 UAH-CPE/EE 422/522 AM 5Review: Clocked JK Flip-FlopNext stateJK = 00 => no state change occursJK = 10 => the flip-flop is set to 1, independent of the current stateJK = 01 => the flip-flop is always reset to 0JK = 11 => the flip-flop changes the state Q+ = Q’01/14/19 UAH-CPE/EE 422/522 AM 6Review: Clocked T Flip-FlopNext stateT = 1 => the flip-flop changes the state Q+ = Q’T = 0 => no state change01/14/19 UAH-CPE/EE 422/522 AM 7Review: S-R Latch, Transparent D-Latch01/14/19 UAH-CPE/EE 422/522 AM 8Mealy Sequential NetworksGeneral model of Mealy Sequential Network(1) X inputs are changed to a new value(2) After a delay, the Z outputs and next state appear at the output of CM(3) The next state is clocked into the state register and the state changes01/14/19 UAH-CPE/EE 422/522 AM 9An Example: 8421 BCD to Excess3 BCD Code ConverterxzQX (inputs) Z (outputs)t3 t2 t1 t0 t3 t2 t1 t00 0 0 0 0 0 1 10 0 0 1 0 1 0 00 0 1 0 0 1 0 10 0 1 1 0 1 1 00 1 0 0 0 1 1 10 1 0 1 1 0 0 00 1 1 0 1 0 0 10 1 1 1 1 0 1 01 0 0 0 1 0 1 11 0 0 1 1 1 0 001/14/19 UAH-CPE/EE 422/522 AM 10State Graph and Table for Code Converter01/14/19 UAH-CPE/EE 422/522 AM 11State Assignment Rules01/14/19 UAH-CPE/EE 422/522 AM 12Transition Table01/14/19 UAH-CPE/EE 422/522 AM 13K-maps01/14/19 UAH-CPE/EE 422/522 AM 14Realization01/14/19 UAH-CPE/EE 422/522 AM 15Sequential Network Timing•Code converter–X = 0010_1001 => Z = 1110_0011Changes in X are not synchronized with active clock edge => glitches (false output), e.g. at tb01/14/19 UAH-CPE/EE 422/522 AM 16Sequential Network Timing (cont’d)Timing diagram assuming a propagation delay of 10 ns for each flip-flop and gate(State has been replaced with the state of three flip-flops)01/14/19 UAH-CPE/EE 422/522 AM 17Setup and Hold Times•For a real D-FF –D input must be stable for a certain amount of time before the active edge of clock cycle => Setup time–D input must be stable for a certain amount of timeafter the active edge of the clock => Hold time•Propagation time: from the time the clock changes to the time the output changesManufacturers provide minimum tsu, th, and maximum tplh, tphl01/14/19 UAH-CPE/EE 422/522 AM 18Maximum Clock Frequencymaxct- Max propagation delay through the combinational networkmaxpt- Max propagation delay from the time the clock changes to the flip-flop output changes { = max(tplh, tphl)}ckt- Clock periodsuckmaxpmaxctttt sumaxpmaxccktttt Example:MHznsfns*tnst,nst,nstmaxckgatesumaxp20501505151521551501/14/19 UAH-CPE/EE 422/522 AM 19Hold Time Violation•Occur if the change in Q fed back through the combinational network and cause D to change too soon after the clock edgehmincminpttt Hold time is satisfied if:What about X?sumaxcxxttt Make sure that input changes propagate to the flip-flops inputs such that setup time is satisfied.Make sure that X does not change too soon after the clock. If X changes at time ty after the active edge, hold time is satisfied ifmincxhyttt 01/14/19 UAH-CPE/EE 422/522 AM 20Moore Sequential NetworksOutputs depend only on present state!))t(Q(F)t(Z x1x2xnz1z2zmZ = z1 z2... zmX = x1 x2... xnQ = Q1 Q2... Qk))t(Q),t(X(G)t(Q Q01/14/19 UAH-CPE/EE 422/522 AM 21General Model of Moore Sequential Machine))t(Q(F)t(Z Inputs(X)ClockZ = z1 z2... zmX = x1 x2... xnQ = Q1 Q2... Qk))t(Q),t(X(G)t(Q Combinational NetworkState RegisterNext StateOutputs depend only on present state!Outputs(Z)State(Q)Combinational Network01/14/19 UAH-CPE/EE 422/522 AM 22Code Converter: Moore MachineS00S11S20S31S40S51S80S71S60S90S1010NCC10NC1C C01NCNCCNCNCStart01100101010101001/14/19 UAH-CPE/EE 422/522 AM 23Code Converter: Moore MachineS00S11S20S31S40S51S80S71S60S90S1010NCC10NC1C C01NCNCCNCNCStart011001010101010Do we need state S0?How many states does Moore machine have?How many states does Mealy machine have?01/14/19 UAH-CPE/EE 422/522 AM 24Moore Machine: State TableS00S11S20S31S40S51S80S71S60S90S1010NCC10NC1C C01NCNCCNCNCStart011001010101010PS NS ZX=0 X=1S0 S1 S2 0S1 S3 S4 1S2 S4 S5 0S3 S6 S7 1S4 S7 S8 0S5 S7 S8 1S6 S9 S10 0S7 S9 S10 1S8 S10 - 0S9 S1 S2 0S10 S1 S2 1Note: state S0 could be eliminated (S0 == S9), if S9 was start state!01/14/19 UAH-CPE/EE 422/522 AM 25Moore Machine Timing•X = 0010_1001 => Z = 1110_0011MooreMealy01/14/19 UAH-CPE/EE 422/522 AM 26State AssignmentsGuidelines to reduce the amount of combinational logicPS NS ZX=0 X=1S0 S1 S2 0S1 S3 S4 1S2 S4 S5 0S3 S6 S7 1S4 S7 S8