Impact of Technology 15 213 Moore s Law Observation by Gordon Moore Intel founder in 1971 Transistors Chip doubles every 18 months Has expanded to include processor speed disk capacity Memory Technology March 15 2001 We Owe a Lot to the Technologists Computer science has ridden the wave Things Aren t Over Yet Topics Technology will continue to progress along current growth curves For at least 7 10 more years Difficult technical challenges in doing so Memory Hierarchy Basics Static RAM Dynamic RAM Magnetic Disks Access Time Gap Even Technologists Can t Beat Laws of Physics Quantum effects create fundamental limits as approach atomic scale Opportunities for new devices class17 ppt class17 ppt Impact of Moore s Law 2 CS 213 S 01 Computer System Moore s Law Performance factors of systems built with integrated circuit technology follow exponential curve E g computer speed memory capacities double every 1 5 years Processor Reg Implications Computers 10 years from now will run 100 X faster Problems that appear intractable today will be straightforward Must not limit future planning with today s technology Cache Memory I O bus Example Application Domains Speech recognition Will be routinely done with handheld devices Breaking secret codes Need to use large enough keys Virtual Reality Complex interactive environments with real time rendering class17 ppt 3 Memory I O controller Disk class17 ppt CS 213 S 01 Page 1 Disk 4 I O controller I O controller Display Network CS 213 S 01 Levels in Memory Hierarchy cache CPU regs Register size speed Mbyte block size C a c h e 8B 200 B 2 ns 8B 32 B Dimensions virtual memory Memory Cache Memory 32KB 4MB 4 ns 100 MB 32 B 128 MB 60 ns 1 00 MB 8 KB 2001 devices 0 18 m 1 cm 8 KB 1 mm 0 1 mm 10 m Chip size 1 cm Disk Memory 30 GB 8 ms 0 05 MB Diameter of Human Hair 25 m 1996 devices 0 35 m 5 0 1 m 10 nm 1 nm 2007 devices 0 1 m Deep UV Wavelength 0 248 m larger slower cheaper class17 ppt 1 m class17 ppt CS 213 S 01 Scaling to 0 1 m 6 Silicon atom radius 1 17 X ray Wavelength 0 6 nm CS 213 S 01 Static RAM SRAM Semiconductor Industry Association 1992 Technology Workshop Projected future technology based on past trends Fast 4 nsec access time 1992 Feature size m 0 5 1995 0 35 1998 0 25 2001 2004 2007 0 18 0 12 0 10 1G 4G 16G Persistent as long as power is supplied no refresh required Industry is slightly ahead of projection DRAM capacity 16M 64M 256M Expensive 100 MByte 6 transistors bit Doubles every 1 5 years Prediction on track Chip area cm2 2 5 4 0 6 0 8 0 10 0 Stable 12 5 High immunity to noise and environmental disturbances Way off Chips staying small class17 ppt Technology for caches 7 1 disk class17 ppt CS 213 S 01 Page 2 8 CS 213 S 01 Anatomy of an SRAM Cell SRAM Cell Principle Inverter Amplifies bit line b bit line b word line 0 1 Terminology bit line word line 6 transistors Negative gain Slope 1 in middle Saturates at ends Stable Configurations 1 Inverter Pair Amplifies 0 1 Positive gain Slope 1 in middle Saturates at ends 0 9 0 8 0 7 0 6 carries data used for addressing 0 5 V1 V2 0 4 Write 0 3 Read 1 set bit lines to new data value b is set to the opposite of b 2 raise word line to high sets cell to new state may involve flipping relative to old state class17 ppt 0 2 1 set bit lines high 2 set word line high 3 see which bit line goes low Vin 0 Stable 10 b7 A0 A1 A2 Ball on Ramp Analogy 0 9 0 6 0 8 1 CS 213 S 01 b7 b1 b1 b0 b0 W0 Require Vin V2 Stable at endpoints recover from pertubation Metastable in middle Fall out when perturbed 1 0 4 Example SRAM Configuration 16 x 8 Stability V2 0 2 Vin class17 ppt CS 213 S 01 Bistable Element V1 0 V2 9 Vin 0 1 V1 W1 Address decoder A3 0 8 memory cells W15 0 7 0 6 Metastable 0 5 Vin 0 4 V2 0 3 sense write amps 0 2 sense write amps sense write amps 0 1 0 0 0 2 Stable class17 ppt 0 4 0 6 0 8 1 Vin 0 11 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 Input output lines 1 class17 ppt CS 213 S 01 Page 3 d7 d1 12 d0 CS 213 S 01 R W Dynamic RAM DRAM Anatomy of a DRAM Cell Word Line Slower than SRAM Bit Line access time 60 nsec Storage Node Access Transistor Not persistent Cnode every row must be accessed every 1 ms refreshed CBL Cheaper than SRAM 1 50 MByte 1 transistor bit Writing Fragile Reading Word Line electrical noise light radiation Workhorse memory technology Word Line Bit Line Bit Line V V Cnode CBL Storage Node class17 ppt 13 class17 ppt CS 213 S 01 Array Size RAS R rows R 2r C columns C 2c N R C bits of memory Addressing address Addresses are n bits where N 2n row address address C leftmost r bits of address col address address C rightmost bits of address r c row col Row address latch 256 Rows 8 Row decoder 256x256 cell array row n 256 Columns column R W sense write amps A7 A0 Example col 0 1 0 000 100 1 001 101 row 1 class17 ppt CS 213 S 01 Example 2 Level Decode DRAM 64Kx1 Addressing Arrays with Bits R 2 C 4 address 6 14 15 2 010 110 Provide 16 bit address in two 8 bit chunks 3 011 111 col 2 Column address latch column latch and decoder 8 CAS class17 ppt CS 213 S 01 Page 4 Dout Din 16 CS 213 S 01 DRAM Operation Observations About DRAMs Row Address 50ns Timing Set Row address on address lines strobe RAS Entire row read stored in column latches Contents of row of memory cells destroyed Access time 60ns cycle time 90ns Need to rewrite row Must Refresh Periodically Column Address 10ns Set Column address on address lines strobe CAS Access selected bit READ transfer from selected column latch to Dout WRITE Set selected column latch to Din Perform complete memory cycle for each row Approximately once every 1ms Sqrt n cycles Handled in background by memory controller Inefficient Way to Get a Single Bit Rewrite 30ns Effectively read entire row of Sqrt n bits Write back entire row class17 ppt 17 class17 ppt CS 213 S 01 Performance Enhanced for Video Graphics Operations Conventional Access RAS Row Col RAS CAS RAS CAS Row Series of columns RAS CAS CAS CAS Gives successive bits Row address latch Frame buffer to hold graphics image 8 Row …
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