EE 308 Apr. 19, 2002Pulse Accumulator on the HC12To use the pulse accumulator connect an input to Port T7The pulse accumulator operates in two modes:1. Event-Count Mode2. Gated Time Accumulation ModeIn Event-Count Mode, the pulse accumulator counts the number of rising orfalling edges on Port T7– You can set up the pulse accumulator to select which edge to count– The counts are held in the 16-bit PACNT register– On each selected edge the PAIF flag of the PAFLG register is set– When PACNT overflows from 0xFFFF to 0x0000, the PAOVF flag of thePAFLG register is setIn Gated Time Accumulation Mode the pulse accumulator counts clock cy-cles while in the input to Port T7 is high or low– In Gated Time Accumulation Mode the pulse accumulator uses the TimerClock. To use the pulse accumulator in Gated Time Accumulation Modeyou must enable the Timer Clock by writing a 1 to the TEN bit of TSCR– You can set up the pulse accumulator to count while PT7 is high or tocount while PT7 is low– The clock for the pulse accumulator is the E-clock divided by 64– With an 8 MHz E-clock the clock frequency of the pulse accumulator is125 kHz, for a period of 8s– For example, if the pulse accumulator is set up to count while Port T7 ishigh, and it counts 729 clock pulses, then the input to Port T7 was highfor 729 x 8s = 5.832 ms1EE 308 Apr. 19, 2002The Pulse AccumulatorThe pulse accumulator uses PT7 as an input– To use the pulse accumulator make sure bit 8 of TIOS is 0 (otherwise PT7used as output compare pin)– To use the pulse accumulator make sure bits 7 and 8 of TCTL1 are 0(otherwise timer function connected to PT7)The pulse accumulator uses three registers: PACTL, PAFLG, PACNTTo use the pulse accumulator you have to program the PACTL registerThe PAFLG register has flags to indicate the status of the pulse accumulator– You clear a flag bit by writing a 1 to that bitThe count value is stored in the 16-bit PACNT register– You may write a value to PACNT– Suppose you want an interrupt after 100 events on PT7– Write -100 to PACNT, and enable the PAOVI interrupt– After 100 events on PT7, PACNT will overflow, and a PAOVI interruptwill be generated0PACTL 0x00A00 PAEN PEDGEPAMOD PAIPAOVICLK1 CLK0PAFLG 0x00A1PAOVF0 0 0 0 0 PAIFPAEN: 1 => Enable PAPAMOD: 0 => Event Count Mode 1 => Gated Time Accumulator ModePEDGE: 0 => Falling Edge (Event) High Enable (Gated) 1 => Rising Edge (Event) Low Enable (Gated)PAOVI: 1 => Enable Interrupt when PACNT overflowsPAI: 1 => Enable Interrupt when edge on PT7 If PEDGE == 0, interrupt on falling edge If PEDGE == 1, interrupt on rising edgeThe 16−bit PACNT register is at address 0x00A22EE 308 Apr. 19, 2002The Pulse AccumulatorE6410PAMODPEDGEPULSE ACCUMULATOR LOGICPACNTPT716 BitPAMOD PAEDGE ACTION 0 1 Increment PACNT on rising edge of PAI 1 0 Count E/64 if PT7 = 1 1 1 Count E/64 if PT7 = 0 0 0 Increment PACNT on falling edge of PAIPAIF(Write)(Write)PAOVFPAIFPAOVF(Read)(Write)DVCCQCLRDVCCQCLR3EE 308 Apr. 19, 2002The Pulse AccumulatorHere is a C program which counts the number of rising edges on PT7:#include "hc12b32.h"#include "DBug12.h"int start_count,end_count,total_count;main(){int i;TIOS = TIOS & ˜0x80; /* PT7 input */TCTL1 = TCTL1 & ˜0xC0 /* Disconnect IC/OC logic from PT7 */PACTL = 0x50; /* 0 1 0 1 0 0 0 0 *//* | | | | | *//* | | | | \_ No interurrupt on edge *//* | | | \___ No interurrupt on overflow *//* | | \_________ Rising Edge *//* | \___________ Event Count Mode *//* \_____________ Enable PA */start_count = PACNT;for (i=0;i<10000;i++) ; /* Software Delay */end_count = PACNT;total_count = end_count - start_count;DBug12FNP->printf("Total counts = %d\r\n",total_count);}4EE 308 Apr. 19, 2002Asynchronous Data TransferIn asynchronous data transfer, there is no clock line between the two devicesBoth devices use internal clocks with the same frequencyBoth devices agree on how many data bits are in one data transfer (usually 8,sometimes 9)A device sends data over an TxD line, and receives data over an RxD line– The transmitting device transmits a special bit (the start bit) to indicatethe start of a transfer– The transmitting device sends the requisite number of data bits– The transmitting device ends the data transfer with a specical bit (the stopbit)The start bit and the stop bit are used to synchronize the data transferVTIdleStartLB0110101 1IdleStopAsynchronous Serial CommunicationsRxD TxDRxDTxDOne byte requires 10 bit timesS0xD6110101105EE 308 Apr. 19, 2002Asynchronous Data TransferThe HC12 has an asynchronous serial interface, called the SCI (Serial Com-munications Interface)The SCI is used by D-Bug12 to communicate with the host PCWhen using D-Bug12 you normally cannot independently operate the SCI (oryou will lose your communications link with the host PC)The D-Bug12 printf() function sends data to the host PC over the SCIThe SCI TxD pin is bit 1 of Port SThe SCI RxD pin is bit 0 of Port SIn asynchronous data transfer, serial data is transmitted by shifting out of atransmit shift register into a receive shift registerSC0DR (Write) SC0DR (Read)TxD Shift Reg RxD Shift RegRxD Shift Reg TxD Shift RegTxDRxD TxDRxDPS1 PS0PS0 PS1SC0DR (Read) SC0DR (Write)Overrun error if RxD shift register filled before SC0DR readSC0DR receive and transmit registers are separate registers.6EE 308 Apr. 19, 2002Timing in Asynchronous Data TransfersThe BAUD rate is the number of bits per secondTypical baud rates are 1200, 2400, 4800, 9600, 19,200, and 115,000At 9600 baud the transfer rate is 9600 bits per second, or one bit in 104sWhen not transmitting the TxD line is held highWhen starting a transfer the trasmitting device sends a start bit by bringingTxD low for one bit perios (104s at 9600 baud)The receiver knows the transmission is starting when it sees RxD go lowAfter the start bit, the trasmitter send the requisite number of data bytesThe receiver checks the data three for each bit. If the data within a bit isdifferent, there is an error. This is called a noise errorThe transmitter ends the transmission with a stop bit, which is a high level onTxD for one bit periodThe reciever checks to make sure that a stop bit is received at the proper timeIf the receiver sees a start bit, but fails to see a stop bit, there is an error.
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