EE 308 Spring 2009Using the HCS12 PWM1. Choose 8-bit mode (PWMCTL = 0x00)2. Choose high polarity (PWMPOL = 0xFF)3. Choose left-aligned (PWMCAE = 0x00)4. Select clock mode in PWMCLK:• PCLKn = 0 for 2N,• PCLKn = 1 for 2(N +1)× M,5. Select N in PWMPRCLK register:• PCKA for channels 5, 4, 1, 0;• PCKB for channels 7, 6, 3, 2.6. If PCLKn = 1, select M• PWMSCLA = M for channels 5, 4, 1, 0• PWMSCLB = M for channels 7, 6, 3, 2.7. Select PWMPERn, normally between 100 and 255.8. Enable desired PWM channels: PWME.9. Select PWMDTYn, normally between 0 and PWMPERn. ThenDuty Cycle n =PWMDTYnPWMPERn× 100%Change duty cycle to control speed of motor or intensity of light, etc.10. For 0% duty cycle, choose PWMDTYn = 0x00.1EE 308 Spring 2009Finding the Values to Set Up the PWM Clock1. Find the number of 24 MHz clock cycles needed for desired PWM frequency:Cycles =24 × 106PWM Frequency2. Choose a vaule for PWMPERx, typically between 100 and 255• To get an e xact frequency, PWMPERx must divide evenly into the number ofcycles found in 1.3. Find the PWM clock period:PWM Clock Period =Total CyclesPWMPERx4. Use either Clock Mode 0 or Clock Mode 1:(a) Clock Mode 0: Find N such that 2N= PWM Clock Period(b) Clock Mode 1: Find M and N such that2N +1× M = PWM Clock Period.Suppose you want a 500 Hz PWM frequency. Then:Cycles =24 × 106500= 48, 000Let’s use PWMPERx = 250. ThenPWM Clock Period =48, 000250= 192Because 192 is not a power of two, we cannot use Clock Mode 0 to get an exact frequency.For Clock Mode 1, we want192 = 2N +1× MWe could do this with N = 0 and M = 96, N = 1 and M = 48, N = 2 and M = 24,and several other combinations.2EE 308 Spring 2009Program to use the MC9S12 PWM System/** Program to generate a 500 Hz PWM on* on Port P Bits 0 and 1** To get 500 Hz, 24,000,000 /500 = 48,000** Choose PWMPERx = 200, then 48,000/200 = 240 = 2^4 x 3 x 5** Lots of ways to set up PWM to achieve this. One way is 2^1 x 120* Choose Clock Mode 1, PCKA = 0, N = 0, PWMSCLA = 120**/#include "hcs12.h"main(){/* Choose 8-bit mode */PWMCTL = 0x00;/* Choose left-aligned */PWMCAE = 0x00;/* Choose high polarity on all channels */PWMPOL = 0xFF;/* Select clock mode 1 for Channels 1 and 0 (no PWMSCLA) */PWMCLK = PWMCLK | (BIT1 | BIT0);/* Select PCKA = 0 for Channels 1 and 0 */PWMPRCLK = (PWMPRCLK & ~0x7);/* Select PWMSCLA = 96 for Channels 1 and 0 */PWMSCLA = 96;/* Select period of 200 for Channels 1 and 0 */PWMPER1 = 200;PWMPER0 = 200;/* Enable PWM on Channels 1 and 0 */PWME = PWME | 0x03;PWMDTY1 = 100; /* 50% duty cycle on Channel 1 */PWMDTY0 = 50; /* 25% duty cycle on Channel 0 */while (1){ /* Code to adjust duty cycle to meet requirements */ }}3EE 308 Spring 2009Analog/Digital Conve rt ers• An Analog-to-Digital (A/D) converter converts an analog voltage into a digital number• There are a wide variety of methods use d for A/D convertersExamples are:– Flash (Parallel)– Successive Approximation– Sigma-Delta– Dual Slope Converter• A/D converters are classified according to several characteristics– Resolution (number of bits) — typically 8 bits to 24 bits– Speed (number of samples per second) — several samples/sec to several billionsamples/sec– Accuracy — how much error there is in the conversion• High-resolution converters are usually slower than low-resolution converters• The MC9S12 has a 10-bit successive approximation A/D converter (which can be usedin 8-bit mode)• The MC9S12 uses an analog multiplexer to allow eight input pins to connect to theA/D converter4EE 308 Spring 2009Comparator• A comparator is used in many types of A/D converters.• A comparator is the simplest interface from an analog signal to a digital signal• A comparator compares two voltage values on its two inputs• If the voltage on the + input is greater than the voltage on the - input, the output willbe a logic high• If the voltage on the + input is less than the voltage on the - input, the output will bea logic lowIf Vin > Vref then Vout = VccIf Vin < Vref then Vout = 0VREFVOUTINVCCV5EE 308 Spring 2009Flash (Paralle l) A/D Converter• A flash A/D converter is the simplest to understand• A flash A/D converter compares an input voltage to a large number of reference voltages• An n-bit flash converter uses 2n-1 comparators• The output of the A/D converter is determined by which of the two reference voltagesthe input signal is between,• Here is a 3-bit A/D converterVin5 V+−+−+−+−+−+−+−4.375 V3.750 V3.125 V2.500 V1.875 V1.250 V0.625 V0.000 VDout6EE 308 Spring 2009Flash A/D Converter• A B-bit Flash A/D converter requires 2B-1 comparators• An 8-bit Flash A/D requires 255 comparators• A 12-bit Flash A/D converter would require 4,095 comparators– Cannot integrate 4,095 comparators onto an IC• The largest flash A/D converter is 8 bits• Flash A/D converters can sample at several billion samples/sec7EE 308 Spring 2009A/D Converter Resolution and Quantization• If the voltage input voltage is 3.2516 V, the lowest 5 comparators will be turned on,and the highest 2 comparators will be turned off• The output of the 3-bit flash A/D converter will be 5 (101)• For a 3-bit A/D converter, which has a range from 0 to 5 V, an output of 5 indicatesthat the input voltage is between 3.125 V and 3.750 V• A 3-bit A/D converter with a 5 V input range has a quantization value of 0.625 V• The quantization value of an A/D converter can be found by∆V =VRH− VRL2bwhere VRHis the highest voltage the A/D converter can handle, VRLis the lowest voltagethe A/D converter can handle, and b is the number of bits of the A/D converter• The MC9S12 has a 10-bit A/D converter. The typical voltage range used for theMC9S12 A/D is VRH= 5 V and VRL= 0 V, so the MC9S12 has a quantization valueof∆V =5 V − 0 V210= 4.88 mV• The dynamic range of an A/D converter is given in decibels (dB):DR(dB) = 20 log 2b= 20blog2 = 6.02b• A 10-bit A/D converter has a dynamic range ofDR(dB) = 6.02 × 10 = 60.2 dB8EE 308 Spring 2009A/D Sampling Rate• The rate at which you sample a signal depends on how rapidly the signal is changing• If you sample a signal too slowly, the information about the signal may be inaccurate9EE 308 Spring 20090 2 4 6 8 10 12 14 16 18 20−1−0.500.51A 1050 Hz signal sampled at 500 Hz0 2 4 6 8 10 12 14 16 18 20−1−0.500.510 2 4 6 8 10 12 14 16 18 20−1−0.500.51t (ms)10EE 308 Spring 2009• A 1,050 Hz signal sampled at 500 Hz looks like a 50 Hz signal• To get full
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