• The 9S12 Serial Peripheral Inteface (SPI) • Huang Section 10.2 through 10.6 • SPI Block User Guide The 9S12 Serial Peripheral Interface (SPI)• The 9S12 has a Synchronous Serial Interface• On the 9S12 it is called the Serial Peripheral Interface (SPI)• Information on the SPI can be found in the SPI Block User Guide.• If an 9S12 generates the clock used for the synchronous data transfer it is operating in Master Mode.• If an 9S12 uses and external clock used for the synchronous data transfer it is operating in Slave Mode.• If two 9S12’s talk to each other using their SPI’s one must be set up as the Master and the other as the Slave.• The output of the Master SPI shift register is connected to the input of the Slave SPI shift register over the Master Out Slave In (MOSI) line.• The input of the Master SPI shift register is connected to the output of the Slave SPI shift register over the Master In Slave Out (MISO) line.• After 8 clock ticks, the data originally in the Master shift register has been transferred to the slave, and the data in the Slave shift register has been transferred to the Master.Synchronous Serial CommunicationsUse of Slave Select with the 9S12 SPI• A master 9S12 can talk with more than one slave 9S12’s• A slave 9S12 uses its Slave Select (SS) line to determine if it is the one the master is talking with• There can only be one master 9S12, because the master 9S12 is the device which generates the serial clock signal.SYNCHRONOUS SERIAL COMMUNICATIONSWith select lines, one master can communicate with more than one slaveUsing the 9S12 SPI• In synchronous serial communications, one device talks to another using a serial data line and a serial clock.• There are a number of decisions to be made before communication can begin.• For example– Is the 9S12 operating in master or slave mode?– Is the serial data sent out most significant bit (MSB) first, or least significant bit (LSB) first?– How many bits are sent in a single transfer cycle?– Is the data valid on the rising edge or the falling edge of the clock?– Is the data valid on the first edge or the second edge of the clock?– What is the speed of the data transfer (how many bits per second)?– Are there two uni-directional data lines or one bi-directional data line?• The 9S12 SPI is very versatile, and allows you to program all of these parameters.• The 9S12 SPI has 5 registers to set up and use the SPI system.SPI0CR1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFESPI0CR2 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0SPI0BR 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0SPI0SR SPIF 0 SPTEF MODF 0 0 0 0SPI0DR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 B IT 2 BIT 1 BIT 0Setting up the 9S12 SPI Clock Mode• You can program the SPI clock to determine the following things:• Is the data valid on the first or the second edge of the clock (clock phase)?• Is the clock idle high or idle low (clock polarity)?• This setup is done in the SPI0CR1 register.Setting up the 9S12 SPI Clock Mode• The speed of the 9S12 clock is set up in the SPI0BR register.• The clock speed is set only if the 9S12 is being used as a master.• The possible clock speeds (for a 24 MHz E-clock) are:SPPR2 SPPR1 SPPR0 SPPR2 SPR1 SPR0 E clockDivisorFrequency at bus clock=24 MHz0000000000000...0000000000000...0000000011111...0000111100001...0011001100110...0101010101010...24816326412825648163264...12.0 MHz6.0 MHz3.0 MHz1.5 MHz750 kHz375 kHz187.5 kHz93.75 kHz6.0 MHz3.0 MHz1.5 MHz750 kHz375 kHz...SPPR2 SPPR1 SPPR0 SPPR2 SPR1 SPR0 E clockDivisorFrequency at bus clock=24 MHz...1111111111111...1111111111111...0000011111111...0111100001111...1001100110011...1010101010101...112224448896179216326412825651210242048...214.29 kHz107.14 kHz53.57 kHz26.78 kHz13.39 kHz1.5 MHz750 kHz375 kHz187.5 kHz93.75 kHz46.87 kHz23.43 kHz11.71 kHzUsing the 9S12 Serial Peripheral InterfaceThings to set up when using the 9S12 SPI subsystem• Enable SPI• Master or Slave?– Master generates clock for data transfers; slave uses master’s clock• MSB first or LSB first?– Normally, MSB first• Clock Polarity– Clock idle low or clock idle high?• Clock Phase– Data valid on first clock edge or second clock edge?• Clock Speed (set by Master)• Generate interrupt after data transferred?• Bidirectional ModeUse the following registers:SPI0CR1 (SPICR1), SPI0CR2 (SPICR2), SPI0BR (SPIBR), SPI0SR (SPISR), SPI0DR (SPIDR)1. Enable SPI (SPE bit of SPI0CR1)2. Clock phase and polarity set to match device communicating with3. Select clock polarity – CPOL bit of SPI0CR1• CPOL = 0 for clock idle low• CPOL = 1 for clock idle high4. Select clock phase – CPHA bit of SPI0CR1• CPHA = 0 for data valid on first clock edge• CPHA = 1 for data valid on second clock edge5. Select master or slave MSTR bit of SPI0CR1• Will be master when talking to devices such as D/A, A/D, clock, etc.• May be slave if talking to another microprocessor6. If you want to receive interrupt after one byte transferred, enable interrupts with SPIE bit of SPI0CR1• Normally master will not use interrupts – transfers are fast enough that you will normally wait for transfer to complete• Will often use interrupts when configured as a slave – you will get interrupt when master sends you data7. Configure LSBF of SPI0CR1 for MSB first (LSBFE = 0) or LSB first (LSBFE = 1)• For most devices, use MSB first8. Configure for uni-directional mode (bit SPC0 = 0) or bi-directional mode(bit SPC0 = 1) in SPI0CR2• Bidirectional mode (SPC0 = 1 in SPI0CR2) used for three-wire communication.• When in bidirectional mode, the BIDIROE bit controls the MOSI and MISO output buffer of the SPI. In master mode this bits controls the output buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port.• BIDIROE = 0 for output buffer disabled• BIDIROE = 1 for output buffer enabled Master Mode:1. Set clock rate – SPPR2:0 and SPR2:0 bits of SPI0BR• Normally select clock at highest rate compatible with slave2. If using bidirectional mode, MOSI pin is used for data (now called MOMI, or Master Out Master In).3. MISO automatically configured as input by choosing master mode4. Configure some way to select slave(s) – probably SS if only one slave; other I/O bits if multiple slaves5. Start data transfer by writing byte to SPI0DR6. After transfer complete (8 clock cycles), SPIF bit of SPI0SR set.• If writing data to slave, can send next byte to SPI0DR• If reading data from
View Full Document
Unlocking...