- The 9S12 in Expanded Mode - Huang Chapter 14Computer with N bit address bus can access 2N bytes of dataComputer with M bit data bus can access M bits of data in one memory cycleValue on address bus tells memory which location computer wants to read (write)Control lines tell memory when computer wants to read (write) data, and if access is read or writeHCS12 has 16 bit address bus − can access 65536 bytes1024 bytes = 1 kB65536 bytes = 64 kBHCS12 has 16 bit data bus − can access 16 bits (2 bytes) at a timeFor example, the instruction LDX $0900will read the two bytes at address $0900 and $0901Sometimes HCS12 only accesses one byte −− e.g., LDAA $0900The HCS12 accesses only the byte at address $0900 __R/W tells memory if HCS12 is reading or writing __R/W high => read__R/W low => writeE tells memory when HCS12 is reading (writing) −− synchronizes data accesses_____LSTRB tells memory if HCS12 accessing one or two bytesAddress, Data and Control Buses• A microprocessor system uses address, data and control buses to communicate with external memory and memory-mapped peripherals• The address bus determines which memory location to access• The control bus specifies whether the memory cycle is a read (into microprocessor) or a write (out of microprocessor) cycle, and specifies timing information for the cycle• The data bus contains the data being transferred during the memory cycle• For example, consider the following simple 9S12 program, which continuously increments the contents of address 0x0400:org 0x2000loop: inc 0x0400bra loop– The program is stored in memory starting at memory location 0x2000– The 9S12 Program Counter starts at address 0x2000– The 9S12 reads the first instruction, inc 0x0400, located in address 0x2000 through 0x2002– The 9S12 then reads the contents of memory location 0x0400, takes an internal memory cycle to increment the value, then writes the new value out to address 0x0400– The 9S12 then reads the next instruction, bra 0x2000– The 9S12 takes one memory cycle to load the program counter with the new value of 0x2000, and to clear its internal pipeline, then reads the instruction at 0x2000 to figure out what to do next.The 9S12 address, data and control buses (simplified)• Note: The following diagram assumes that the 9S12 accesses one byte at a time• The 9S12 actually accesses two bytes (16 bits) at a time, when it can• What actually occurs on the 9S12 bus is a little more complicated than what is shown belowADDRESS, DATA AND CONTROL BUS (SIMFLIFIED)The 9S12 Memory Map• The 9S12 has address regions occupied by internal memory and peripherals• A diagram showing which address regions are used is called a memory map• Here is a memory map of the 9S12DP256 with no added memory or peripherals0x00000x03FFRegisters 1 KB0x04000x0FFFEEPROM 3 KB0x10000x3BFFUserRAM11 KB0x3C000x3FFFD-Bug 12RAM1 KB0x40000x7FFFFlashEEPROM16 KB0x80000xBFFFFlashEEPROM16 KB0xC0000xFFFFD-Bug 12FlashEEPROM16 KBThe Expanded 9S12 Memory Map• We will add external peripherals to the 9S12• Here is a memory map of the MC9S12DP256 with the peripherals we will add• The peripherals will be put at 0x4054 and 0x40550x00000x03FFRegisters 1 KB0x04000x0FFFEEPROM 3 KB0x10000x3BFFUserRAM11 KB0x3C000x3FFFD-Bug 12RAM1 KB0x40000x7FFFUnusedSpaceUse address 0x4000-0x4001For external peripherals0x80000xBFFFFlashEEPROM16 KB0xC0000xFFFFD-Bug 12FlashEEPROM16 KBSimplified 9S12 Write Cycle• When the 9S12 writes data to memory it does the following:– It puts the address it wants to write to on the address bus (when E-clock goes low)– It puts the data it wants to write onto the data bus– It brings the Read/Write (R/W) line low to indicate a write– The 9S12 expects the external device at the given address will latch the data into its registers data on the falling edge of the E-clockWRITE: a) HCS12 puts address on address bus and puts data on data bus __b) brings R/W lowc) Memory latches data on falling edge of E clockExample: Write 0xfedc to address 0x3456 & 3457Simplified 9S12 Read Cycle• When the 9S12 reads data from memory it does the following:– It puts the address it wants to read from on the address bus (when E-clock goes low)– It brings the Read/Write (R/W) line high to indicate a read– The 9S12 expects the external device at the given address will put data on the data bus– On the falling edge of the E-clock, the 9S12 latches the data into its internal register.READ: a) HCS12 puts address on address bus __b) brings R/W highc) Memory puts data on data bus HCS12 latches data on falling edge of E clockExample: Read from address 0x5678 & 0x5679The Real MC9S12DG256 Bus• Up to now we have been using the 9S12 in Single Chip Mode– In Single Chip Mode the 9S12 does not have an external address/data bus• The 9S12 can be run in Expanded Mode– In Expanded Mode the 9S12 does have an external address/data bus• Things are a little more complicated on the real MC9S12DG256 bus than shown in the simplified diagrams above• The MC9S12DG256 has a multiplexed address/data bus• The MC9S12DG256 sometimes accesses a single byte on a memory cycle, and it sometimes access two bytes on a memory cycleThe Multiplexed Address/Data Bus• The MC9S12DG256 has a limited number of pins it can use• To have full 16-bit address bus and a full 16-bit data bus the MC9S12DG256 would need to use 32 extra pins (in addition to several pins used for the control bus)• To save pin count Motorola uses the same set of pins for several purposes• When put into expanded mode, the 9S12 uses the pins normally used for Ports A and B for its mulitplexed address and data bus– When running in expanded mode you can no longer use Ports A and B as general purpose I/O lines• The 9S12 uses the same sixteen line of Ports A and B for both addressand data• When the E-clock is low the sixteen lines AD15-0 are used for address• When the E-clock is high the sixteen lines AD15-0 are used for dataHCS12 has 16−bit address and 16−bit data busesRequires 35 bits Not enough pins on HCS12 to allocate 35 pins for buses and pins for all other functionsMemory Chip Interface• Memory chips need separate address and data bus– Need way to de-multiplex address and data lines from 9S12• Memory chips need different control lines than the 9S12 supplies• These control lines are:– Chip Select – goes low when the 9S12 is accessing memory chip– Write Enable –
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