EE 308 Spring 2011 Review for Exam III Analog/Digital Converters • Methods used for A/D converters – Flash (Parallel) – Successive Approximation • A/D converters are classified according to: – Resolution (number of bits) – Speed (number of samples per second) • The MC9S12 has two 10-bit successive approximation A/D converters - can be used in 8-bit mode • The MC9S12 uses an analog multiplexer to allow eight input pins to connect to any of the A/D converters • The quantization level of the A/D converter ∆V = (VRH − VRL)/2b • There are inputs on the HCS12 for the reference voltages VRL and VRH – In normal operation VRL = 0 V and VRH = 5 V. – You must have VSS ≤ VRL < VRH ≤ VDD. • Register that need to use to set up the A/D subsystem: ATD1CTL2 ATD1CTL3 Control Regs ATD1CTL4 ATD1CTL5 ATD1STAT0 Status RegEE 308 Spring 2011 The MC9S12 IIC Interface • The IIC bus can control multiple devices using only two wires – The two wires are Clock and Data – The lines are normally high. Any device on the bus can bring them low. • Each device on the bus has a unique address • An IIC master starts the process by sending out a serial stream with the seven-bit address of the slave it wants to talk to, and an eighth bit indicating if it wants to write to the slave or read from the slave • If it writes to the slave, it will continue to send data on the serial data line until all the data is sent. • If it reads from the slave, it will release the data line, and activate the clock line. The slave takes over the data line, and sends out its data in response to the clock provided by the master. • After all of the data is transferred, the master releases both the clock and the data linesEE 308 Spring 2011 The MC9S12 in Expanded Mode • MC9S12 uses Ports A and B as mulitplexed address/data bus In expanded mode, you can no longer use Ports A and B for I/O • 16−bit Bus: While E low, bus supplies address (from MC9S12) While E high, bus supplies data (from MC9S12 on write, From memory on read) • When the MC9S12 writes data to memory: 1. Puts address on the address bus (when E-clock goes low) 2. Brings the Read/Write (R/W) line low 3. Puts the data it wants to write onto the data bus 4. External device needs to latch the data on falling edge of the E-clock • When the MC9S12 reads data to memory: 1. Puts address on the address bus (when E-clock goes low) 2. Brings the Read/Write (R/W) line high 3. MC9S12 expects external device to put data on the data bus 4. External device needs to latch the data on falling edge of the E-clock LSTRB A0 Type of Access 0 0 16-bit access of an even address Accesses bytes at even address and subsequent odd address 0 1 8-bit access of an odd address 1 0 8-bit access of an even address 1 1 Not allowed on external busEE 308 Spring 2011 • The MC9S12 in Expanded Mode – Timing • Huang Chapter 14 Using the MC9S12 Expanded Bus — Timing Issues • In expanded mode, memory and peripherals can be added to the MC9S12. • In order for the expansion to work, the interface timing must be correct. • Here we will discuss adding more RAM memory to the MC9S12. • It is necessary to look at the timing of the MC9S12, the “glue logic” (the chips between the MC9S12 and the memory) and the memory to see if all the specs are met. • Below we will analyze the timing issues for the external memory, and find out what frequency of MC9S12 bus clock is needed to be able to use the external RAM. • The RAM we will evaluate is a 55 ns Samsung K6T1008C2E (128Kx8 bit Low Power CMOS Static RAM)EE 308 Spring 2011 • The interface uses 18 address lines (A17-0). The MC9S12 allows you to use more than 16 address lines by paging the memory. You select a memory page with Port K, and use a CALL and RTC (Return from CALL) instructions to switch pages. – The PPAGE register keeps the page value, which is written to Port K. It allows up to 256 16kB program memory pages to be switched into and out of the program memory window. This provides up to 4 MB of paged program memory space) – The CALL instruction pushes the 16-bit return address and the current 8-bit page register (PPAGE) onto the stack and then transfers control to the subroutine (3 bytes are pushed onto the stack). CALL <opr> is a instruction designed to work with expanded memory. The MC9S12 treat the 16-kB memory space from $8000 to $BFFF as a program memory window. The <opr> field in the call instruction specifies the page number and the starting address of the subroutine within that page. The new page number is loaded into PPAGE when the call instruction is executed. – The RTC (Return from Call) terminates subroutines in expanded mode invoked by the CALL instruction and pulls the return address and page register from the stack. • The Samsung K6T1008C2E RAM require the following signals:EE 308 Spring 2011EE 308 Spring 2011EE 308 Spring 2011 Bus clock frequency needed for memory expansion • The control signals for the memory are generated by the MC9S12 and the glue logic. • With a 24 MHz bus clock, the time E-clock is high is about 21 ns. • The memory chip needs the address stable for 55 ns before it can get the data out of its memory. • The memory cannot work with an MC9S12 using a 24 MHz clock. • With an 8 MHz oscillator, the MC9S12 can use a bus clock of 8 MHz, 16 MHz or 24 MHz. • To have the address stable for 55 ns, the clock period must be greater than 110 ns, which corresponds to a 9 MHz frequency. • To have the address stable for 55 ns, the bus clock frequency must be less than 9 MHz. The expansion board uses an 8 MHz bus clock. • With an 8 MHz clock, the clock period is 125 ns. E is high for about 62 ns, and low for about 62 ns. • Assume 3 ns for signals to propagate through the glue logic chips.EE 308 Spring 2011EE 308 Spring 2011EE 308 Spring 2011 Memory Read • CS for even memory chip 1. E goes low 2. 8 ns later, AD15-0 change into address (MC9S12 spec) 3. 3 ns later, A15-0 comes out of 74AHC573 (glue logic) 4. CS goes low 11 ns after E goes low. (Total) • CS for odd chip is LSTRB; CS for odd chip goes low 7 ns after E goes low • Output Enable (OE) 1. E goes high 2. 3 ns later, OE goes low (glue logic) 3. OE goes low 3 ns after E goes high (Total) • Valid Data from …
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