EE 308 Lab 11 Spring 2002EE 308 – LAB 11Memory Expansion for the HC12In this lab you will will add external memory to your HC12. You will be given a daughter board which willplug into the header pins on your HC12 EVBU. The daughter board has an Altera EPM7128S chip whichwill function as the address latch and memory decoder needed for the memory expansion. This week youwill program the Altera chip to enable the memory expansion. Next week you will add code to the Alterachip to add two general purpose I/O ports.The attached schematic shows how the Altera chip and RAM chip are connected. Note that the lines betweenthe Altera chip and the HC12 are:AD15-0 Ports A and B Port E1 Port E2Port E3E Port E4The lines connected to the RAM chip are:AD15-0A16-0 Note that the the RAM chip uses 16 address lines to select one ofdata words (64 kW), while the HC12uses 16 address lines to select one ofdata bytes (64 kB). The RAM chip uses its(High ByteEnable) and(Low Byte Enable) lines to distinguish between bytes within a data word. Thus, theaddress lines for the HC12 and the RAM do not quite match. It is necessary to connect address line A1 fromthe HC12 to address line A0 of the RAM; A2 from the HC12 to A1 of the RAM, etc. Use A0 from theHC12 to of the RAM to select the high (even) byte. Usefrom the HC12 toof the RAMto select the low (odd) byte.Note that on the schematic that there is something called the JTAG interface. This is simply some circuitrywhich will allow you to program the Altera chip through the parallel port of your computer.1. Complete the attached Altera GDF file to finish the memory expansion. (You can do it as a TDF fileif you prefer.) About all you need to do is to assign the pinouts of the Altera chip to match the pinoutsshown in the schematic. We are not going to have the Altera chip interrupt the HC12 at this time, soyou should add to the Altera file something which will drive the! line out of the HC12 high. Also,you have to figure out what you should do with the A16 line out of the Altera chip (which goes to theA15 line of the RAM).The port expansion next week will require the use of the RESET line from the HC12, which will beconnected to Pin 89 of the Altera chip. You should add a RESET input pin to the GDF (or TDF) file,and assign it to Pin 89 to reserve this pin.1EE 308 Lab 11 Spring 20022. Compile your Altera program and download it into the Altera chip on your memory expansion board.Your lab instructor will show you how to do this. (Also, have your lab instructor check your Alteraprogram and pinouts. It is possible to damage the Altera chip, the RAM chip, and/or the HC12 if thepin assignments are incorrect.)3. Put the HC12 into expanded mode. To do this, put the following program into EEPROM at address0x0D00:CLR $0016 ; Disable COPMOVB #$2C,$000A ; Enable LSTRB, R/W and EBSET $000B,#$68 ; Expanded wide mode, turn on internal visibilityBCLR $0013,#$0C ; Put in zero E-Clock stretchesJMP $F700 ; Jump to DBug-12Move the jumpers so the HC12 will run from EEPROM. Reset the HC12. Verify you are in expandedmode by using DBug-12 to examine the contents of the PEAR, MODE and MISC registers. Recordthe values of these three registers, and show that the HC12 is in expanded mode, that LSTRB, R/Wand E are enabled, and that there are zero E-clock stretches.4. Verify that you can access the expanded memory. Use DBug-12 to do a Block Fill of memory from0x1000 to 0x7FFF. First fill it with 0x55, then 0xAA (alternating patterns of 0 and 1). If this works,your memory expansion is probably okay.5. Take your HC12 to a logic analyzer. Connect the following lines to the logic analyzer: AD3-0,AD15-12, LSTRB, R/W, and E. (There are not enough pins on the logic analyzer to connect allthe address/data and control lines from the HC12). Set up the logic analyzer to use the fastest clockpossible. Use DBug-12 to enter the following simple program into memory starting at address 0x2000:movw #$aa55,$0000movb #$cc,$0002movb #$dd,$0003bra $2000This program will do a 16-bit access of an even address, an 8-bit access of an even address, and an8-bit access of an odd address. Capture a waveform while this program is running. Show that anE-clock cycle takes about 125 ns. Identify the three types of memory access, and verify that LSTRB,A0, and R/W are what they should be. Also, verify that the Address/Data lines display the addresswhen E is low, and data when E is high. (Note: The results may be a bit ambiguous because of thetime it takes for AD15-0 to switch from data to address after E goes low, and the time it takes forAD15-0 to switch from address to data after E goes high.) The logic analyzer is not fast enough toallow you to make accurate timing measurements to compare to the specifications in the data sheet,but should be fast enough to show the functioning of the address/data and control buses.2EE 308 Lab 11 Spring 2002123456ABCD654321DCBATitleNumberRevisionSizeBDate:3-Apr-2002 Sheet of File:C:\ACADEMIC\EE308\SPR02\308DBD.DdbDrawn By:C60.1uFC40.1uFC30.1uFC70.1uFC10.1uFV3.5C90.1uFC80.1uFC20.1uFV3.512345678910P3JTAG_inNote: The JTAG_IN requires a special cable. See cable schematic in order to make the correct cable to program the Altera chip. The Cable will plug onto the board through the JTAG_IN connector and plug into the Parallel port on the computer. Then follow the Altera instruction on programing Altera chips via JTAG.WECS_MEMA1A16A2A3A4A5A6A7A8A9A10A11A12A14A13A15OEA0BLEC50.1uF12345678161514131211109RP133
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