EE 308 Spring 2009Using the HCS12 Expanded Bus — Timing Issues• In expanded mode, memory and peripherals can be added to the HCS12.• In order for the expansion to work, the interface timing must be correct.• Here we will discuss adding more RAM memory to the HCS12.• It is necessary to look at the timing of the HCS12, the “glue logic” (the chips betweenthe HCS12 and the memory) and the memory to see if all the specs are met.• Below we will analyze the timing issues for the external memory, and find out whatfrequency of HCS12 bus clock is needed to be able to use the external RAM.• The RAM we will evaluate is a 55 ns Samsung K6T1008C2E• Note that the interface uses 18 address lines (A17-0). The M C9S12 allows you to usemore than 16 address lines by paging the memory. You select a memory page withPort K, and use a CALL and RTC (Return from CALL) instructions to switch pages.– The PPAGE register keeps the page value, which is written to Port K.– The CALL instruction pushes the 16-bit return address and the current 8-bit pageregister onto the stack, then loads the address register and page register with newvalues.– The RTC instruction pulls the return address and page register from the stack.1EE 308 Spring 2009Schematic of Memory Expansion74AHC574R/WR/WLSTRBHCS12K6T1008EAD7−0 (Port B)D7−0OEOEWEWECSCSAD15−8 (Port A) D15−8Port AEPort KPort BA17−1A16−0A16−0A0C2EE 308 Spring 200974AHC574Valid Data55 ns10 ns20 nsAddressCSOEDataREAD CYCLER/WR/WLSTRBHCS12K6T1008EAD7−0 (Port B)D7−0OEOEWEWECSCSAD15−8 (Port A) D15−8Port AEPort KPort BA17−1A16−0A16−0A0C3EE 308 Spring 2009Bus clock frequency needed for memory expansion• The control signals for the memory are generated by the HCS12 and the glue logic.• With a 24 MHz bus clock, the time E-clock is high is about 21 ns.• The memory chip needs the address stable for 55 ns before it can get the data out ofits memory.• The memory cannot work with an HCS12 using a 24 MHz clock.• With a 4 MHz oscillator, the HCS12 can use a bus clock of 4 MHz, 8 MHz, 12 MHz,16 MHz, 20 MHz or 24 MHz.• To have the address stable for 55 ns , the clock period must be greater than 110 ns,which corresponds to a 9 MHz frequency.• To have the address stable for 55 ns, the bus clock frequency must be less than 9 MHz.The expansion board uses an 8 MHz bus clock.• Assume 3 ns for signals to propagate through the glue logic chips.4EE 308 Spring 2009MC9S12DP256B Device User Guide — V02.13120Figure A-9 General External Bus TimingAddr/Data(read)Addr/Data(write)addrdatadata5 10118166ECLK1, 23 4addrdatadata12159714 13ECS2120 22 23Non-Multiplexed1719LSTRB29NOACC32IPIPO0IPIPO1, PE6,5351827283033363134R/W242625AddressesPE4PA, PBPA, PBPK5:0PK7PE2PE3PE75EE 308 Spring 2009MC9S12DP256B Device User Guide — V02.13121Table A-20 Expanded Bus Timing CharacteristicsConditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pFNum C Rating Symbol Min Typ Max Unit1 P Frequency of operation (E-clock)fo0 25.0 MHz2 P Cycle timetcyc40 ns3 D Pulse width, E lowPWEL19 ns4 DPulse width, E high1PWEH19 ns5 D Address delay timetAD8 ns6 DAddress valid time to E rise (PWEL–tAD) tAV11 ns7 D Muxed address hold timetMAH2 ns8 D Address hold to data validtAHDS7 ns9 D Data hold to addresstDHA2 ns10 D Read data setup timetDSR13 ns11 D Read data hold timetDHR0 ns12 D Write data delay timetDDW7 ns13 D Write data hold timetDHW2 ns14 DWrite data setup time1 (PWEH–tDDW)tDSW12 ns15 DAddress access time1(tcyc–tAD–tDSR)tACCA19 ns16 DE high access time1(PWEH–tDSR)tACCE6 ns17 D Non-multiplexed address delay timetNAD6 ns18 DNon-muxed address valid to E rise (PWEL–tNAD) tNAV15 ns19 D Non-multiplexed address hold timetNAH2 ns20 D Chip select delay timetCSD16 ns21 DChip select access time1 (tcyc–tCSD–tDSR)tACCS11 ns22 D Chip select hold timetCSH2 ns23 D Chip select negated timetCSN8 ns24 D Read/write delay timetRWD7 ns25 DRead/write valid time to E rise (PWEL–tRWD) tRWV14 ns26 D Read/write hold timetRWH2 ns27 D Low strobe delay timetLSD7 ns28 DLow strobe valid time to E rise (PWEL–tLSD) tLSV14 ns29 D Low strobe hold timetLSH2 ns30 D NOACC strobe delay timetNOD7 ns31 DNOACC valid time to E rise (PWEL–tNOD) tNOV14 ns6EE 308 Spring 2009Memory Read• CS for even memory chip1. E goes low2. 8 ns later, AD15-0 change into address (HCS12 spec)3. 3 ns later, A15-0 comes out of 74AHC573 (glue logic)4. 6 ns later, CS goes low for even memory chip. (glue logic)5. CS goes low 17 ns after E goes low. (Total)• CS for odd chip about same; CS for odd chip goes low 14 ns after E goes low• Output Enable (OE)1. E goes high2. 3 ns later, OE goes low (glue logic)3. OE goes low 3 ns after E goes high (Total)• Valid Data from Memory1. E goes low2. 8 ns later, AD15-0 change into address (HCS12)3. 3 ns later, A15-0 comes out of 74AHC573 (glue logic)4. 55 ns later, valid data is available from memory chip (memory)5. 66 ns after E goes low, valid data is available (but not on bus) (Total)• Data from Memory put onto bus1. E goes high2. 3 ns later, OE goes low (glue logic)3. 25 ns later, memory chip puts data onto bus (memory)4. 28 ns after E goes low, data from memory is put onto bus (total)7EE 308 Spring 2009• HCS12 reads data1. HCS12 needs data on bus 13 ns before E goes low (HCS12)2. E goes low 62 ns - 28 ns = 34 ns before E goes low (Total)3. This meets the HCS12 data setup time• Data removed from bus1. HCS12 needs data on bus 0 ns after E goes low (HCS12)2. OE goes high 3 ns after E goes low (glue logic)3. Data removed from bus 0 to 20 ns after OE goes high (memory)4. Data on bus 3 ns to 23 ns after E goes low (Total)5. This meets the HCS12 data hold time• The memory chip will work with the RAM for read cyclesOEAddressDataAD15−0E62 ns 62 nsValid DataADDRESSHi−ZADDRESS28 ns 34 ns 3 to 23 nsR/WCSLSTRB8EE 308 Spring 200974AHC574R/WR/WLSTRBWRITE CYCLEAddressCSWEDataData Valid45 ns20 ns 0 nsHCS12K6T1008EAD7−0 (Port B)D7−0OEOEWEWECSCSAD15−8 (Port A) D15−8Port AEPort KPort BA17−1A16−0A16−0A0C9EE 308 Spring 2009Memory Write• CS for even memory chip1. E goes low2. 8 ns later, AD15-0 change into address (HCS12)3. 3 ns later, A15-0 comes out of 74AHC573 (glue logic)4. 6 ns later, CS goes low for even memory chip. (glue logic)5. CS goes low 17 ns after E goes low (Total)• CS for odd chip about same; CS for odd chip goes low 14 ns after E goes low• Write Enable (WE)1. E goes high2. 3 ns later, WE goes low (glue logic)3.
View Full Document
Unlocking...