EE 308 Spring 2009USING INTERRUPTS ON THE HCS12What happens when the HCS12 receives an unmasked interrupt?1. Finish current instruction2. Push all registers onto the stack3. Set I bit of CCR4. Load Program Counter from interrupt vector for highest priority interrupt which ispendingThe following (from the MC9S12DP256B Device User Guide) shows the exceptionpriorities. The Reset is the highest priority, the Clock Monitor Fail Reset the nexthightest, etc.1EE 308 Spring 2009MC9S12DP256B Device User Guide — V02.1377Section 5 Resets and Interrupts5.1 OverviewConsult the Exception Processing section of the HCS12 Core User Guide for information on resets andinterrupts.5.2 Vectors5.2.1 Vector TableTable 5-1 lists interrupt sources and vectors in default order of priority.Table 5-1 Interrupt Vector LocationsVector Address Interrupt SourceCCRMaskLocal EnableHPRIO Valueto Elevate$FFFE, $FFFF Reset None None –$FFFC, $FFFD Clock Monitor fail reset None PLLCTL (CME, SCME) –$FFFA, $FFFB COP failure reset None COP rate select –$FFF8, $FFF9 Unimplemented instruction trap None None –$FFF6, $FFF7 SWI None None –$FFF4, $FFF5 XIRQ X-Bit None –$FFF2, $FFF3 IRQ I-Bit IRQCR (IRQEN) $F2$FFF0, $FFF1 Real Time Interrupt I-Bit CRGINT (RTIE) $F0$FFEE, $FFEF Enhanced Capture Timer channel 0 I-Bit TIE (C0I) $EE$FFEC, $FFED Enhanced Capture Timer channel 1 I-Bit TIE (C1I) $EC$FFEA, $FFEB Enhanced Capture Timer channel 2 I-Bit TIE (C2I) $EA$FFE8, $FFE9 Enhanced Capture Timer channel 3 I-Bit TIE (C3I) $E8$FFE6, $FFE7 Enhanced Capture Timer channel 4 I-Bit TIE (C4I) $E6$FFE4, $FFE5 Enhanced Capture Timer channel 5 I-Bit TIE (C5I) $E4$FFE2, $FFE3 Enhanced Capture Timer channel 6 I-Bit TIE (C6I) $E2$FFE0, $FFE1 Enhanced Capture Timer channel 7 I-Bit TIE (C7I) $E0$FFDE, $FFDF Enhanced Capture Timer overflow I-Bit TSRC2 (TOF) $DE$FFDC, $FFDD Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC$FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA$FFD8, $FFD9 SPI0 I-Bit SP0CR1 (SPIE, SPTIE) $D8$FFD6, $FFD7 SCI0 I-BitSC0CR2(TIE, TCIE, RIE, ILIE)$D6$FFD4, $FFD5 SCI1 I-BitSC1CR2(TIE, TCIE, RIE, ILIE)$D4$FFD2, $FFD3 ATD0 I-Bit ATD0CTL2 (ASCIE) $D2$FFD0, $FFD1 ATD1 I-Bit ATD1CTL2 (ASCIE) $D0$FFCE, $FFCF Port J I-Bit PTJIF (PTJIE) $CE$FFCC, $FFCD Port H I-Bit PTHIF(PTHIE) $CC$FFCA, $FFCB Modulus Down Counter underflow I-Bit MCCTL(MCZI) $CA2EE 308 Spring 2009MC9S12DP256B Device User Guide — V02.13785.3 Effects of ResetWhen a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to therespective module Block User Guides for register reset states.5.3.1 I/O pinsRefer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out ofreset.Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.$FFC8, $FFC9 Pulse Accumulator B Overflow I-Bit PBCTL(PBOVI) $C8$FFC6, $FFC7 CRG PLL lock I-Bit CRGINT(LOCKIE) $C6$FFC4, $FFC5 CRG Self Clock Mode I-Bit CRGINT (SCMIE) $C4$FFC2, $FFC3 BDLC I-Bit DLCBCR1(IE) $C2$FFC0, $FFC1 IIC Bus I-Bit IBCR (IBIE) $C0$FFBE, $FFBF SPI1 I-Bit SP1CR1 (SPIE, SPTIE) $BE$FFBC, $FFBD SPI2 I-Bit SP2CR1 (SPIE, SPTIE) $BC$FFBA, $FFBB EEPROM I-Bit EECTL(CCIE, CBEIE) $BA$FFB8, $FFB9 FLASH I-Bit FCTL(CCIE, CBEIE) $B8$FFB6, $FFB7 CAN0 wake-up I-Bit CAN0RIER (WUPIE) $B6$FFB4, $FFB5 CAN0 errors I-Bit CAN0RIER (CSCIE, OVRIE) $B4$FFB2, $FFB3 CAN0 receive I-Bit CAN0RIER (RXFIE) $B2$FFB0, $FFB1 CAN0 transmit I-Bit CAN0TIER (TXEIE2-TXEIE0) $B0$FFAE, $FFAF CAN1 wake-up I-Bit CAN1RIER (WUPIE) $AE$FFAC, $FFAD CAN1 errors I-Bit CAN1RIER (CSCIE, OVRIE) $AC$FFAA, $FFAB CAN1 receive I-Bit CAN1RIER (RXFIE) $AA$FFA8, $FFA9 CAN1 transmit I-Bit CAN1TIER (TXEIE2-TXEIE0) $A8$FFA6, $FFA7 CAN2 wake-up I-Bit CAN2RIER (WUPIE) $A6$FFA4, $FFA5 CAN2 errors I-Bit CAN2RIER (CSCIE, OVRIE) $A4$FFA2, $FFA3 CAN2 receive I-Bit CAN2RIER (RXFIE) $A2$FFA0, $FFA1 CAN2 transmit I-Bit CAN2TIER (TXEIE2-TXEIE0) $A0$FF9E, $FF9F CAN3 wake-up I-Bit CAN3RIER (WUPIE) $9E$FF9C, $FF9D CAN3 errors I-Bit CAN3RIER (TXEIE2-TXEIE0) $9C$FF9A, $FF9B CAN3 receive I-Bit CAN3RIER (RXFIE) $9A$FF98, $FF99 CAN3 transmit I-Bit CAN3TIER (TXEIE2-TXEIE0) $98$FF96, $FF97 CAN4 wake-up I-Bit CAN4RIER (WUPIE) $96$FF94, $FF95 CAN4 errors I-Bit CAN4RIER (CSCIE, OVRIE) $94$FF92, $FF93 CAN4 receive I-Bit CAN4RIER (RXFIE) $92$FF90, $FF91 CAN4 transmit I-Bit CAN4TIER (TXEIE2-TXEIE0) $90$FF8E, $FF8F Port P Interrupt I-Bit PTPIF (PTPIE) $8E$FF8C, $FF8D PWM Emergency Shutdown I-Bit PWMSDN (PWMIE) $8C$FF80 to$FF8BReserved3EE 308 Spring 2009Most interrupts have both a specific mask and a general mask. For most interrupts thegeneral mask is the I bit of the CCR. For the TOF interrupt the specific mask is the TOIbit of the TSCR2 register.Before using interrupts, make sure to:1. Load stack pointer• Done for you in C by the C startup code2. Write Interrupt Service Routine• Do whatever needs to be done to service interrupt– You cannot pass a variable to an ISR. If the ISR needs to know the value of avariable used in another part of the program, that variable must be global– You cannot return a variable from an ISR to another part of the program. Ifthe program needs to know the value of a variable set in an ISR, that variablemust be global• Clear interrupt flag• Exit with the RTI instruction– Use the INTERRUPT key word in the Gnu C compiler– Tells compiler to exit function with rti instruction rather than rts instruction3. Load address of interrupt service routine into interrupt vector• E.g., UserTimerOvf = (unsigned short) &toi_isr;4. Do any setup needed for interrupt• For example, for the TOF interrupt, turn on timer and set prescaler5. Enable specific interrupt6. Enable interrupts in general (clear I bit of CCR with cli instructionCan disable all (maskable) interrupts with the sei instruction.• Gnu C turns on interrupts be default (in startup code, where stack pointer is loaded)• Should turn off interrupts before doing setup.• Can do this with asm(" sei");• Can also do the following:#define disable() asm(" sei")#define enable() asm(" cli")and then use more C-like disable(); and enable();4EE 308 Spring 2009Example of C program us ing Timer Overflow Interrupt#include <hcs12.h>#include <vectors12.h>#include "DBug12.h"#define enable() asm(" cli")#define disable() asm(" sei")void INTERRUPT toi_isr(void); /* Function prototype */main(){disable();DDRB = 0xff; /* Make Port B output *//* Setup for Timer Overflow Interrupt */TSCR1 = 0x80; /* Turn on timer
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