EE 308 Spring 2010Exam 1Feb. 24• You will be able to us e all of the c lass handouts from the Motorola data manuals onthe exam, and one page of notes.• No calculators will be allowed for the exam.• Numbers– Decimal to Hex (signed and unsigned)– Hex to Decimal (signed and unsigned)– Binary to Hex– Hex to Binary– Addition and subtraction of fixed-length hex numb ers– Overflow, Carry, Zero, Negative bits of CCR• Programming Model– Internal registers – A, B, (D = AB), X, Y, SP, PC, CCR• Addressing M odes and Effective Addresses– INH, IMM, DIR, EXT, REL, IDX (Not Indexed Indirect)– How to determine effective address• Instructions– What they do - Core Users Guide– What machine code is generated– How many cycles to execute– Effe ct on CCR– Branch instructions – which to use with signed and which with unsigned• Machine Code– Reverse Assembly• Stack and Stack Pointer– What happens to stack and SP for instructions (e.g., PSHX, JSR)– How the SP is used in getting to and leaving subroutines• Asse mbly Language– Be able to read and write simple assembly language program– Know basic assembler directives – e.g., equ, dc.b, ds.w– Flow charts1EE 308 Spring 2010An MC9S12 has the following data in its memory:0 1 2 3 4 5 6 7 8 9 A B C D E F10D0 10 23 3B 7C 10 04 86 80 B7 10 25 3B FC 10 18 F310E0 10 F5 FD 10 18 86 40 B7 10 23 3B FC 10 12 DD 0210F0 86 CE A2 53 1A 2F A3 10 03 86 40 B7 10 25 3B 86Determine the contents of the A and X register after executing the following code frag-ments. (Before the first instruction, the X register has $0000.) List the values in hexadecimal.Also, indicate what addressing mode is used, and what the effective address of the instruc-tion is. (Assume that the first instruction is at address $2000, and that the instructions thatfollow are in subsequent locations – i.e., the instruction of (a) takes two bytes, so the firstinstruction of (b) is at address $2002.)a. ldaa #43b. ldaa $10E7c. ldx $10E0ldaa -2,Xd. ldx #$10E0ldaa -2,Xe. ldx #$10E0ldaa 2,+Xf. ldx #$10E0ldaa 2,X+2EE 308 Spring 2010An MC9S12 has the following data in its memory:0 1 2 3 4 5 6 7 8 9 A B C D E F10D0 10 23 3B 7C 10 04 86 80 B7 10 25 3B FC 10 18 F310E0 10 F5 FD 10 18 86 40 B7 10 23 3B FC 10 12 DD 0210F0 86 CE A2 53 1A 2F A3 10 03 86 40 B7 10 25 3B 86Determine the contents of the A and X register after executing the following c ode frag-ments. (Before the first instruction, the X register has $0000.) List the values in hexadecimal.Also, indicate what addressing mode is used, and what the effective address of the instruc-tion is. (Assume that the first instruction is at address $2000, and that the instructions thatfollow are in subsequent locations – i.e., the instruction of (a) takes two bytes, so the firstinstruction of (b) is at address $2002.)a. 2000: ldaa #43 Op code: 86 43LDAA #43 located at address $2000Addressing mode: IMM, Effective address: $2001 (PC + 1)A: $2B, X: $0000b. 2002: ldaa $10E7 Op code: B6 10 E7Addressing mode: EXT, Effective address: $10E7A: $B7, X: $0000 (A loads contents 0f $10E7)c. 2005: ldx $10E02008: ldaa -2,X Op code: FE 10 E0 A6 1Eldx addressing mode: EXT, Effective address: $10E0ldaa addressing mode: IDX, Effective address: $10F3A: $53, X: $10F5X loads contents of $10E0, which puts $10F5 into XA loads contents of ($01F5 - 2 = $10F3), which puts $53 into Ad. 200A: ldx #$10E0200D: ldaa -2,X Op code: CE 10 E0 A6 1Eldx instruction located at address $200Aldx addressing mode: IMM, Effective address: $200Bldaa addressing mode: IDX, Effective address: $10DEA: $18, X: $10E0X is loaded with $10E0A loads contents of ($01E0 - 2 = $10DE), which puts $18 into A3EE 308 Spring 2010e. 200F: ldx #$10E02012: ldaa 2,+X Op code: CE 10 E0 A6 21ldx instruction located at address $200Fldx addressing mode: IMM, Effective address: $2010ldaa addressing mode: IDX, Effective address: $10E2A: $FD, X: $10E2X is loaded with $10E0A loads contents of ($01E0 + 2 = $10E2), which puts $FD into AX is pre-incremented to $10E2f. 2014: ldx #$10E02017: ldaa 2,X+ Op code: CD 10 E0 A6 31ldx instruction located at address $2014ldx addressing mode: IMM, Effective address: $2015ldaa addressing mode: IDX, Effective address: $10E0A: $10, X: $10E2X is loaded with $10E0A loads contents of $01E0, which puts $10 into AX is post-incremented to $10E24EE 308 Spring 2010USING INTERRUPTS ON THE MC9S12What happens when the MC9S12 receives an unmasked interrupt?a. Finish current instructionb. Push all registers onto the stackc. Set I bit of CCRd. Load Program Counter from interrupt vector for highest priority interrupt which ispendingThe following (from the MC9S12DP256B Device User Guide) shows the exceptionpriorities. The Reset is the highest priority, the Clock Monitor Fail Reset the nexthightest, etc.5EE 308 Spring 2010MC9S12DP256B Device User Guide — V02.1377Section 5 Resets and Interrupts5.1 OverviewConsult the Exception Processing section of the HCS12 Core User Guide for information on resets andinterrupts.5.2 Vectors5.2.1 Vector TableTable 5-1 lists interrupt sources and vectors in default order of priority.Table 5-1 Interrupt Vector LocationsVector Address Interrupt SourceCCRMaskLocal EnableHPRIO Valueto Elevate$FFFE, $FFFF Reset None None –$FFFC, $FFFD Clock Monitor fail reset None PLLCTL (CME, SCME) –$FFFA, $FFFB COP failure reset None COP rate select –$FFF8, $FFF9 Unimplemented instruction trap None None –$FFF6, $FFF7 SWI None None –$FFF4, $FFF5 XIRQ X-Bit None –$FFF2, $FFF3 IRQ I-Bit IRQCR (IRQEN) $F2$FFF0, $FFF1 Real Time Interrupt I-Bit CRGINT (RTIE) $F0$FFEE, $FFEF Enhanced Capture Timer channel 0 I-Bit TIE (C0I) $EE$FFEC, $FFED Enhanced Capture Timer channel 1 I-Bit TIE (C1I) $EC$FFEA, $FFEB Enhanced Capture Timer channel 2 I-Bit TIE (C2I) $EA$FFE8, $FFE9 Enhanced Capture Timer channel 3 I-Bit TIE (C3I) $E8$FFE6, $FFE7 Enhanced Capture Timer channel 4 I-Bit TIE (C4I) $E6$FFE4, $FFE5 Enhanced Capture Timer channel 5 I-Bit TIE (C5I) $E4$FFE2, $FFE3 Enhanced Capture Timer channel 6 I-Bit TIE (C6I) $E2$FFE0, $FFE1 Enhanced Capture Timer channel 7 I-Bit TIE (C7I) $E0$FFDE, $FFDF Enhanced Capture Timer overflow I-Bit TSRC2 (TOF) $DE$FFDC, $FFDD Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC$FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA$FFD8, $FFD9 SPI0 I-Bit SP0CR1 (SPIE, SPTIE) $D8$FFD6, $FFD7 SCI0 I-BitSC0CR2(TIE, TCIE, RIE, ILIE)$D6$FFD4, $FFD5 SCI1 I-BitSC1CR2(TIE, TCIE, RIE, ILIE)$D4$FFD2, $FFD3 ATD0 I-Bit
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