- The 9S12 in Expanded Mode - External Ports - Huang Chapter 14Accessing External Memory and Ports on the 9S12 in ExpandedMode• In expanded mode, the 9S12 has a multiplexed 16-bit address and data bus.• With a 16-bit address bus, the 9S12 can access 216 = 65, 536 bytes of data• With a 16-bit data bus, the 9S12 can access 16 bits (two bytes) in a single bus cycle• In expanded mode, the 9S12 uses Port A and Port B as the multiplexed address/data bus• Timing is controlled by the E clock• When the E clock is low, the 9S12 places the address on the multiplexed bus– Port A is used for address bits 15-8– Port B is used for address bits 7-0• When the E clock is high, the 9S12 uses the multiplexed bus for data bus:– Port A is used for the even byte– Port B is used for the odd byteFor example, if accessing the sixteen-bit word at address 0x4000 (the bytes at addresses 0x4000 and 0x4001), Port A will access the byte at address 0x4000, and Port B will access the byte at address 0x4001.• Sometimes you only want to access one byte at a time. For example,– ldaa $4001will access the single byte at address 0x4001.• To determine whether it should access one byte or two bytes, the 9S12 ______uses the LSTRB and A0 lines. ______– LSTRB low means that the 9S12 is accessing the lower (odd) byte of a sixteen-bit word ______– LSTRB high means that the 9S12 is accessing the upper (even) byte of a sixteen-bit word– A0 low means that the 9S12 is accessing the upper (even) byte– A0 high means that the 9S12 is accessing the lower (odd) byte_____LSTRBA0 Type of Access0011010116-bit access of an even addressAccesses bytes at even address and subsequent odd address8-bit access of an odd address8-bit access of an even addressNot allowed on external bus• The instruction– ldaa $4000accesses the byte at address 0x4000, but doesn’t access the byte at address 0x4001. For this access, the 9S12 will put 0x4000 on the bus (A0 = 0, access even byte), and will _____make LSTRB = 1 (don’t access odd byte).• The instruction– ldaa $4001accesses the byte at address 0x4001, but doesn’t access the byte at address 0x4000. For this access, the 9S12 will put 0x4001 on the bus (A0 = 1, access odd byte), and will make_____LSTRB = 0 (access odd byte).• The instruction– ldd $4000accesses the bytes at addresses 0x4000 and 0x4001. For this access, the 9S12 will put _____ 0x4000 on the bus (A0 = 0, access even byte), and will make LSTRB = 0 (access odd byte).Simple Parallel Input Port• We want a port which will read 8 bits of data from the outside• Such a port is similar to Port A or Port B when all pins are set up as input• We need some hardware to drive the input data onto the data bus at the time the 9S12 needs it to be there to read it• The hardware needs to keep the data off the bus at all other times so it doesn’t interfere with data from other devices• A tri-state buffer can be used for this purpose– A tri-state buffer has three output states: logic high, logic low, and high impedance (high-Z)– In high-Z state it is like the buffer is not connected to the output at all, so another device can drive the output– a tri-state output acts like a switch — when the switch is closed, the output logic level is the same as the input logic level, and when the switch is open, the buffer does not change the logic level on the output pin– A tri-state buffer has a control input which, when active, drives the input logic levels onto the output pins, and when inactive, opens the switch.(b) Equivalent circuit(c) Truth table x f e (a) A tri-state buffer0 0 1 1 0 1 0 1 Z Z 0 1 f e x x f e = 0e = 1x f f x e (d) ImplementationA Simple Parallel Input Port• When should the tri-state buffer be enabled to drive the data bus?– The 9S12 will access the buffer by reading from an address. We must assign an address for the tri-state buffer– We must have hardware to demultiplex the address from the data, and to determine when the 9S12 is reading from this address– The 8-bit input will be connected to 8 bits of the 16-bit address/data bus of the 9S12_ If the address of the input is even, we need to connect the output of the buffer to the even (high) byte of the bus, which is connected to AD15-8 (what was Port A)_ If the address of the input is odd, we need to connect the output of the buffer to the odd (low) byte of the bus, which is connected to AD7-0 (what was Port B)– The 9S12 needs the data on the bus on the high-to-low transition of the E-clock– We must enable the tri-state buffer when1. The address of the buffer is on the address bus2. The 9S12 is reading from this address3. The 9S12 is reading the high byte if the address is even, or the low byte if the address is odd4. E is high• For example, consider an input port at address 0x4000 (an even address, or high byte):Multiplexer built using a decoder and tri-state buffersw1w0w0Eny0w1y1y2y3fs0s11w2w3A Simple Parallel Output Port• We want a port which will write 8 bits of data to the outside• Such a port is similar to Port A or Port B when all pins are set up as output• We need some hardware to latch the output data at the time the 9S12 puts the data on the data bus• We can use a set of 8 D flip-flops to latch the data– The D inputs will be connected to the data bus– The clock to latch the flip-flops should make its low-to-high transition when the 9S12 has the appropriate data on the bus– The 9S12 will access the flip-flops by writing to an address. We must assign an address for the tri-state buffer– We must have hardware to demultiplex the address from the data, and to determine when the 9S12 is writing to this addressExample: Read from address 0x4000E __R/WA/D 0x4000ADDR 0x4000__CSPort APort BHCS12LATCHA/D 15-8A/D 7-0ADDR = 0x4000 __R/W = 1E = 1E __R/WLSTRBExternalData__CSADDR(16)– The 8-bit inputs of the D flip-flops will be connected to 8 bits of the 16-bit address/data bus of the 9S12_ If the address of the input is even, we need to connect the flip flop inputs to the even (high) byte of the bus, which is connected to AD15-8 (what was Port A)_ If the address of the input is odd, we need to connect the flip flop inputs to the odd (low) byte of the bus,
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