Chapter 1 Serial Communications Interface (S12SCIV2) Block Description1.1 Introduction1.1.1 Glossary1.1.2 Features1.1.3 Modes of Operation1.1.3.1 Run Mode1.1.3.2 Wait Mode1.1.3.3 Stop Mode1.1.4 Block Diagram1.2 External Signal Description1.2.1 TXD-SCI Transmit Pin1.2.2 RXD-SCI Receive Pin1.3 Memory Map and Registers1.3.1 Module Memory Map1.3.2 Register Descriptions1.3.2.1 SCI Baud Rate Registers (SCIBDH and SCHBDL)1.3.2.2 SCI Control Register 1 (SCICR1)1.3.2.3 SCI Control Register 2 (SCICR2)1.3.2.4 SCI Status Register 1 (SCISR1)1.3.2.5 SCI Status Register 2 (SCISR2)1.3.2.6 SCI Data Registers (SCIDRH and SCIDRL)1.4 Functional Description1.4.1 Data Format1.4.2 Baud Rate Generation1.4.3 Transmitter1.4.3.1 Transmitter Character Length1.4.3.2 Character Transmission1.4.3.3 Break Characters1.4.3.4 Idle Characters1.4.4 Receiver1.4.4.1 Receiver Character Length1.4.4.2 Character Reception1.4.4.3 Data Sampling1.4.4.4 Framing Errors1.4.4.5 Baud Rate Tolerance1.4.4.5.1 Slow Data Tolerance1.4.4.5.2 Fast Data Tolerance1.4.4.6 Receiver Wakeup1.4.4.6.1 Idle Input Line Wakeup (WAKE = 0)1.4.4.6.2 Address Mark Wakeup (WAKE = 1)1.4.5 Single-Wire Operation1.4.6 Loop Operation1.5 Initialization Information1.5.1 Reset Initialization1.5.2 Interrupt Operation1.5.2.1 System Level Interrupt Sources1.5.2.2 Interrupt Descriptions1.5.2.2.1 TDRE Description1.5.2.2.2 TC Description1.5.2.2.3 RDRF Description1.5.2.2.4 OR Description1.5.2.3 IDLE Description1.5.3 Recovery from Wait ModeFreescale Semiconductor 1 Chapter 1 Serial Communications Interface (S12SCIV2) Block Description1.1 Introduction This block guide provide an overview of serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs.1.1.1 GlossaryIRQ — Interrupt RequestLSB — Least Significant BitMSB — Most Significant BitNRZ — Non-Return-to-ZeroRZI — Return-to-Zero-InvertedRXD — Receive PinSCI — Serial Communication InterfaceTXD — Transmit Pin1.1.2 FeaturesThe SCI includes these distinctive features:• Full-duplex operation• Standard mark/space non-return-to-zero (NRZ) format • 13-bit baud rate selection• Programmable 8-bit or 9-bit data format • Separately enabled transmitter and receiver• Programmable transmitter output parity• Two receiver wake up methods:— Idle line wake-up— Address mark wake-up• Interrupt-driven operation with eight flags:— Transmitter emptySerial Communications Interface (S12SCIV2) Block Description2 Freescale Semiconductor — Transmission complete— Receiver full — Idle receiver input— Receiver overrun— Noise error— Framing error — Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection 1.1.3 Modes of OperationThe SCI operation is the same independent of device resource mapping and bus interface mode. Different power modes are available to facilitate power saving. 1.1.3.1 Run ModeNormal mode of operation.1.1.3.2 Wait ModeSCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. • If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. • If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI.1.1.3.3 Stop ModeThe SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI module clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI.Serial Communications Interface (S12SCIV2) Block DescriptionFreescale Semiconductor 3 1.1.4 Block DiagramFigure 1-1 is a high level block diagram of the SCI module, showing the interaction of various functional blocks.Figure 1-1. SCI Block Diagram1.2 External Signal DescriptionThe SCI module has a total of two external pins:1.2.1 TXD-SCI Transmit PinThis pin serves as transmit data output of SCI.1.2.2 RXD-SCI Receive PinThis pin serves as receive data input of the SCI. SCI DATA REGISTERRECEIVE SHIFT REGISTERRECEIVE & WAKE UP CONTROLDATA FORMAT CONTROLTRANSMIT CONTROLTRANSMIT SHIFT REGISTERSCI DATA REGISTERBAUDGENERATORRX DATA IN÷16BUS CLOCKTXDATA OUTIDLE IRQRDR/OR IRQTDRE IRQTC IRQORINGIRQ GENERATIONIRQ GENERATIONIRQTO CPUSerial Communications Interface (S12SCIV2) Block Description4 Freescale Semiconductor 1.3 Memory Map and RegistersThis section provides a detailed description of all memory and registers.1.3.1 Module Memory MapThe memory map for the SCI module is given below in Figure 1-2. The Address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register.1.3.2 Register DescriptionsThis section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register location do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order.Address Name Bit 7 6 5 4 3 2 1 Bit 00x0000 SCIBDHR 0 0 0SBR12 SBR11 SBR10 SBR9 SBR8W0x0001 SCIBDLRSBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0W0x0002 SCICR1RLOOPS SCISWAI RSRC M WAKE ILT PE PTW0x0003 SCICR2RTIE TCIE RIE ILIE TE RE RWU SBKW0x0004 SCISR1R TDRE TC RDRF IDLE OR NF FE PFW0x0005 SCISR2R 0 0 0 0 0BRK13 TXDIRRAFW0x0006 SCIDRHR R8T80 0 0 0 0 0W0x0007 SCIDRLR R7 R6 R5 R4 R3 R2 R1 R0W T7 T6 T5 T4 T3 T2 T1 T0= Unimplemented or ReservedFigure 1-2. SCI Register SummarySerial Communications Interface (S12SCIV2) Block DescriptionFreescale Semiconductor 5 1.3.2.1 SCI Baud Rate Registers (SCIBDH and SCHBDL)The SCI Baud Rate Register is used by the counter to determine the baud rate of the SCI. The formula for calculating the baud rate is:SCI baud rate = SCI module clock / (16 x BR)where:BR
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