EE 308 Spring 2010Lecture 16February 27, 2012Interrupts on the MC9S12The Real Time InterruptInterrupt vectors for the MC9S12• The interrupt vectors for the MC9S12DP256 are located in memory from 0xFF80 to0xFFFF.• These vectors are programmed into Flash EEPROM and are very difficult to change• DBug12 redirects the interrupts to a region of RAM where they are easy to change• For example, when the MC9S12 gets a TOF interrupt:– It loads the PC with the contents of 0xFFDE and 0xFFDF.– The program at that address tells the MC9S12 to look at address 0x3E5E and0x3E5F.– If there is a 0x0000 at these two addresses, DBug12 gives an error stating that theinterrupt vector is uninitialized.– If there is anything else at these two addresses, DBug12 loads this data into thePC and executes the routine located there.– To use the TOF interrupt you need to put the address of your TOF ISR at ad-dresses 0x3E5E and 0x3E5F.• The location of the vectors is defined in include files so you don’t have to rememberthem or look them up in the reference manual.– For Assembly programs, the vectors are defined in the file hcs12.incUserTimerOvf equ $3E5E– For C programs, the vectors are defined in the file vectors12.h#define UserTimerOvf _VEC16(47) /* Maps to 0x3E5E */1EE 308 Spring 2010Commonly Used Interrupt Vectors for the MC9S12DP256Interrupt Specific General Normal DBug-12Mask Mask Vector VectorSPI2 SP2CR1 (SPIE, SPTIE) I FFBC, FFBD 3E3C, 3E3DSPI1 SP1CR1 (SPIE, SPTIE) I FFBE, FFBF 3E3E, 3E3FIIC IBCR (IBIR) I FFC0, FFC1 3E40, 3E41BDLC DLCBCR (IE) I FFC2, FFC3 3E42, 3E43CRG Self Clock Mode CRGINT (SCMIE) I FFC4, FFC5 3E44, 3E45CRG Lock CRGINT (LOCKIE) I FFC6, FFC7 3E46, 3E47Pulse Acc B Overflow PBCTL (PBOVI) I FFC8, FFC9 3E48, 3E49Mod Down Ctr UnderFlow MCCTL (MCZI) I FFCA, FFCB 3E4A, 3E4BPort H PTHIF (PTHIE) I FFCC, FFCD 3E4C, 3E4DPort J PTJIF (PTJIE) I FFCE, FFCF 3E4E, 3E4FATD1 ATD1CTL2 (ASCIE) I FFD0, FFD1 3E50, 3E51ATD0 ATD0CTL2 (ASCIE) I FFD2, FFD3 3E52, 3E53SCI1 SC1CR2 I FFD4, FFD5 3E54, 3E55(TIE, TCIE, RIE, ILIE)SCI0 SC0CR2 I FFD6, FFD7 3E56, 3E57(TIE, TCIE, RIE, ILIE)SPI0 SP0CR1 (SPIE) I FFD8, FFD9 3E58, 3E59Pulse Acc A Edge PACTL (PAI) I FFDA, FFDB 3E5A, 3E5BPulse Acc A Overflow PACTL (PAOVI) I FFDC, FFDD 3E5C, 3E5DEnh Capt Timer Overflow TSCR2 (TOI) I FFDE, FFDF 3E5E, 3E5FEnh Capt Timer Channel 7 TIE (C7I) I FFE0, FFE1 3E60, 3E61Enh Capt Timer Channel 6 TIE (C6I) I FFE2, FFE3 3E62, 3E63Enh Capt Timer Channel 5 TIE (C5I) I FFE4, FFE5 3E64, 3E65Enh Capt Timer Channel 4 TIE (C4I) I FFE6, FFE7 3E66, 3E67Enh Capt Timer Channel 3 TIE (C3I) I FFE8, FFE9 3E68, 3E69Enh Capt Timer Channel 2 TIE (C2I) I FFEA, FFEB 3E6A, 3E6BEnh Capt Timer Channel 1 TIE (C1I) I FFEC, FFED 3E6C, 3E6DEnh Capt Timer Channel 0 TIE (C0I) I FFEE, FFEF 3E6E, 3E6FReal Time CRGINT (RTIE) I FFF0, FFF1 3E70, 3E71IRQ IRQCR (IRQEN) I FFF2, FFF3 3E72, 3E73XIRQ (None) X FFFF, FFFF 3E74, 3E75SWI (None) (None) FFF6, FFF7 3E76, 3E77Unimplemented Instruction (None) (None) FFF8, FFF9 3E78, 3E79COP Failure COPCTL (None) FFFA, FFFB 3E7A, 3E7B(CR2-CR0 COP Rate Select)COP Clock Moniotr Fail PLLCTL (CME, SCME) (None) FFFC, FFFD 3E7C, 3E7DReset (None) (None) FFFE, FFFF 3E7E, 3E7F2EE 308 Spring 2010EXCEPTIONS ON THE MC9S12• Exceptions are the way a processor responds to things other than the normal sequenceof instructions in memory.• Exceptions consist of such things as Reset and Interrupts.• Interrupts allow a processor to respond to an event without constantly polling to seewhether the event has occurred.• On the MC9S12 some interrupts cannot be masked — these are the UnimplementedInstruction Trap and the Software Interrupt (SWI instruction).• XIRQ interrupt is masked with the X bit of the Condition Code Register. Once the Xbit is cleared to enable the XIRQ interrupt, it cannot be set to disable it.– The XIRQ interrupt is for external events such as power fail which must be re-sponed to.• The rest of the MC9S12 interrupts are masked with the I bit of the CCR.– All these other interrupts are also masked with a specific interrupt mask. Forexample, the Timer Overflow Interrupt is masked with the TOI bit of the TSCR2register.– This allows you to enable any of these other interrupts you want.– The I bit can be set I to 1 to disable all of these interrupts if needed.3EE 308 Spring 2010The Real Time Interrupt• Like the Timer Overflow Interrupt, the Real Time Interrupt allows you to interrupt the processor at a regular interval.• Information on the Real Time Interrupt is in the CRG Block User Guide• There are two clock sources for MC9S12 hardware.– Some hardware uses the Oscillator Clock. The RTI system uses this clock.∗ For our MC9S12, the oscillator clock is 8 MHz.– Some hardware uses the Bus Clock. The Timer system (including the Timer Overflow Interrupt) use this clock.∗ For our MC9S12, the bus clock is 24 MHz.InterruptI BitCCR. .1, 2, 4, 8, 16, 32, 64. .. .D QVCCWriteRTIFReadRTIFRTIE BitRTR 6:4 (RTICTL)1, 2, 3, 4, . . ., 16RTR 3:0 (RTICTL)2OSC Clock108 MHzCRGINTCRGFLG4EE 308 Spring 2010• The specific interrupt mask for the Real Time Interrupt is the RTIE bit of the CRGINTregister.• When the Real Time Interrupt occurs, the RTIF bit of the CRGFLG register is set.– To clear the Real Time Interrupt write a 1 to the RTIF bit of the CRGFLGregister.• The interrupt rate is set by the RTR 6:4 and RTR 2:0 bits of the RTICTL register.The RTR 6:4 bits are the Prescale Rate Select bits for the RTI, and the RTR 2:0 bitsare the Modulus Counter Select bits to provide additional graunularity.RTIF 0PORF LOCKIF LOCK TRACK SCMIF SCM00x0037 CRGFLG0x0038 CRGINTRTIE LOCKIE SCMIE0 0 0 0RTR0RTR6 RTR5 RTR1 0x003B RTICTLRTR3 RTR20 RTR4• To use the Real Time Interrupt, set the rate by writing to the RTR 6:4 and the RTR 3:0bits of the RTICTL, and enable the interrupt by setting the RTIE bit of the CRGINTregister– In the Real Time Interrupt ISR, you need to clear the RTIF flag by writing a 1 tothe RTIF bit of the CRGFLG register.5EE 308 Spring 2010• The following table shows all possible values, in ms, selectable by the RTICTL register(assuming the system uses a 8 MHz oscillator):RTR 3:0 RTR 6:4000 001 010 011 100 101 110 111(0) (1) (2) (3) (4) (5) (6) (7)0000 (0) Off 0.128 0.256 0.512 1.024 2.048 4.096 8.1920001 (1) Off 0.256 0.512 1.204 2.048 4.096 8.192 16.3840010 (2) Off 0.384 0.768 1.536 3.072 6.144 12.288 24.5760011 (3) Off 0.512 1.024 2.048 4.096 8.192 16.384 32.7680100 (4) Off 0.640 1.280 2.560
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