EE 308 - L18 - Mar. 7 and 17, 2003The HCS12 Pulse Width Modulation SystemPERDTYPulse Width ModulationControl speed of motor by adjusting percentof time power is applied to the motor.Need to choose period, and have a way to adjustduty cycleThe HCS12 has a flexible, and complicated, PWM systemThere are eight 8-bit PWM channels– Two 8-bit channels can be combined into a single 16-bit channel– We will discuss only 8-bit modeYou can select center-aligned or left-aligned PWM– We will discuss only left-aligned modeYou can select high polarity or low polarity– We will discuss only high polarity mode1EE 308 - L18 - Mar. 7 and 17, 2003The HCS12 Pulse Width Modulation SystemThere are 32 registers you need to program to set up the eight channels of thePWMTo select 8-bit mode, write a 0 to Bits 7, 6, 5, and 4 of PWMCTL registerTo select left-aligned mode, write a 0 to Bit n of PWMCAE registerTo select high polarity mode, write a 1 to Bit n of PWMPOL registerTo set the period for a PWM channel you need to program bits in the follow-ing PWM registers– For Channels 0, 1, 4, and 5 the registers are PWMPOL, PWMCLK, PWMPRCLK, PWMCAE,PWMCTL, and PWMSCLA.– For Channels 2, 3, 6, and 7 the registers are PWMPOL, PWMCLK, PWMPRCLK, PWMCAE,PWMCTL, and PWMSCLB.To set the period for a PWM channel you need to write to the PWMPER registerfor that channelTo set the duty cycle for a PWM channel you need to write to the PWMDTYregister for that channel2EE 308 - L18 - Mar. 7 and 17, 2003Set PWEMn =1 to enable PWM on CHn 0x00A1 PWMPOLPPOL7If PWEMn = 0, the Port P bit can be used as general purpose I/O PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0PPOLn − Choose polarity. 1 = > high polarity. 0 = > low polarity. 0x00A2 PWMCLKPCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0PCLKn − Choose clock source for channel n CH7, CH6, CH3, CH2 can use either B(0) or SB(1) CH5, CH4, CH1, CH0 can use either A(0) or SA(1) B ASB = SA =0x00A3 PWMPRCLKPCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 0 0 This register selects the prescale clock source for clocks A and B independently We will use high polarity only . Duty cycle will be the amount of time PCKA[2−0]: Prescaler for Clock APCKB[2−0]: Prescaler for Clock BDivide 24 MHz clock by 2Divide 24 MHz clock by 2PCKA[2−0]PCKB[2−0]2 x (PWMSCLB) the output is high. M 0x00A0 PWMEPWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0PWMPOL = PWMPOL | 0xFF;2 x (PWMSCLA) 3EE 308 - L18 - Mar. 7 and 17, 2003Bit 7 6 5 4 3 2 1 Bit 0Bit 7 6 5 4 3 2 1 Bit 00x00A8 PWMSCLA0x00A9 PWMSCLBPWMSCLA adjusts frequency of Clock SAPWMSCLB adjusts frequency of Clock SBCON67 00 0x00A5 PWMCTLCONxy − Concatenate PWMx and PWMy into one 16 bit PWMCON45 CON23 CON01 PSWAI PFRZChoose PWMCAE = 0x00 to choose left aligned mode Select center aligned outputs (1) or left aligned outputs (0)CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 0x00A4 PWMCAEChoose PWMCTL = PWMCTL & ~0XF0 to choose 8−bit mode PWM Period = (PWMPERn) x Period of PWM Clock nPWMPERn sets period of CHnPWMDTYn adjusts duty cycle of CHnPWM Duty Cycle = (PWMDTYn)/(PWMPERn) x 100%4EE 308 - L18 - Mar. 7 and 17, 20032PCKA201PCLK0CLK0CompareCLK0Ch0 PeriodPCKA=PCKA + 1PCLK0 = 0PCLK0 = 1Clock Select for PWM Channel 0You need to set PCKA, PWMSCLA, PCLK0, and PWMPER024 MHz Clock(PWMSCLA)PWMCNT0PWMPER0PWMCNT0 counts from 0 to PWMPER0 − 1It takes PWMPER0 periods of CLK0 to make one Ch0 periodCh0 Period = ( PWMPER0 ) x CLK0 Period( PWMPER0) x (2 )( PWMPER0) x (2 ) x (PWMSCLA)5EE 308 - L18 - Mar. 7 and 17, 2003How to set the Period for PWM Channel 0To set the period for PWM Channel 0:– Set the PWM Period register for Channel 0, PWMPER0– CLK0, the clock for Channel 0, drives a counter (PWMCNT0)– In left aligned output mode PWMCNT0 counts from 0 to the value in theperiod register PWMPER0 - 1.– The period for PWM Channel 0 is (PWMPER0)Period of CLK0There are two modes for the clock for PWM Channel 0– You select the mode by the PCLK0 bit in the PWMCLK register– If PCLK0 == 0, CLK0 is generated by dividing the 24 MHz clock by , where PCKA is between 0 and 7– If PCLK0 == 1, CLK0 is generated by dividing the 24 MHz clock by(PWMSCLA), where PCKA is between 0 and 7 and PWMSCLAis between 0 and 255The Period for PWM Channel 0 (in number of 41.67 ns cycles) is calculatedby ! #"%$ &'%( )+*-,/.10 2#345687! #"%$ &'%()+*-,/./! #"%$:9;2#3<%(10 2#3456 =With PCLK0 == 0, the maximum possible PWM period is 1.36 msWith PCLK0 == 1, the maximum possible PWM period is 0.695 s6EE 308 - L18 - Mar. 7 and 17, 2003To get a 0.5 ms PWM period, you need 12,000 cycles.=777 ;"%$ &%'()+*-,/.10 2#345687 ;"%$ &%'()+*-,/./ ;"%$:9;23#<%(10 2#3456 =You can do this in many ways– With PCLK0 = 0, can havePCKA PWMPER06 187 Close7 93 Close– With PCLK0 = 1, can havePCKA PWMSCLA PWMPER00 24 250 Exact0 25 240 Exact0 30 200 Exact0 40 150 Exact0 50 120 Exact1 12 250 Exact1 15 200 Exact2 6 250 Exact2 10 150 Exact3 3 250 Exactand many other combinations7EE 308 - L18 - Mar. 7 and 17, 2003You want PWMPER0 to be large (say, 100 or larger)– If PWMPER0 is small, you don’t have much control over the duty cycle– For example, if PWMPER0 = 4, you can only have 0%, 25%, 50%, 75%or 100% duty cycleOnce you choose a way to set the PWM period, you can program the PWMregistersFor example, to get a 0.5 ms period, let’s use PCLK0 = 1, PCKA = 0,PWMSCLA = 30, and PWMPER0 = 200We need to do the following:– Write 0 to Bits 7,6,5, and 4 of PWCLK (to set up 8-bit mode)– Write 0 to Bits 2,1,0 of PWMCLK (to set PCKA to 0)– Write 1 to Bit 0 of PWMCLK (to set PCLK0 = 1)– Write 1 to Bit 0 of PWMPOL (to select high polarity mode)– Write 30 to PWMSCLA– Write 0 to Bit 0 of PWMCAE (to select left aligned mode)– Write 200 to PWMPER0– Write 1 to Bit 0 of PWME (to enable PWM on Channel 0)– Write the appropriate value to PWMDTY0 to get the desired duty cycle(e.g., PWMDTY0 = 120 will give 60% duty cycle)8EE 308 - L18 - Mar. 7 and 17, 2003C code to set up PWM Channel 0 for 0.5 ms period (2 kHz frequency) PWMwith
View Full Document
Unlocking...