EE 308 Spring 2011 • Using the MC9S12 IIC Bus with DS 1307 Real Time Clock • DS1307 Data Sheet • Asynchronous Serial Communications • The MC9S12 Serial Communications Interface (SCI) • MC9S12 SCI Block Guide V02.05 • Huang, Sections 9.2-9.6 Lab on IIC Bus •Lab on the IIC Bus 1. Communicate with Dallas Semiconductor DS 1307 Real Time Clock (a) Set time and date in clock (b) Read time and date from clock and display 2. Display time and date on LCD display • Hardest program this semester • Need to use functions • How to write to LCD display discussed in a previous class notes char msg[] = "hello, world!"; openlcd(); while (1) { msg1 = "..."; put2lcd(0x80,CMD); // Move to first line puts2lcd(msg1); msg2 = "..."; put2lcd(0xC0,CMD); // Move to second line puts2lcd(msg2); } • Need C functions to write to and read from RTC over the IIC bus • Notes from March 24 have functions to initialize IIC bus (iic_init()), start a transfer by writing address and R/Wbit (iic_start()), transmit a byte of data (iic_transmit()), and stop the transfer (release IIC bus, iic_stop()). • Need C functions to switch to receive mode (iic_swrcv()) and receive data over IIC bus (iic_receive).EE 308 Spring 2011 • Need to put functions together to write to the RTC, read from the RTC, and display the time/date on the LCD display • To write data to LCD display, data has to be in the form of an ASCII string • Data from RTC is in form of BCD data • For example, year is 0x09 msg[0] = ((year>>4)&0x0f) + ’0’; msg[1] = ((year)&0x0f) + ’0’; msg[2] = ’/’; ... msg[8] = 0; put2lcd(0x80,CMD); // Move to first line puts2lcd(msg);EE 308 Spring 2011 Lab on IIC Bus • To read data from RTC, need to do the following: – Put IIC bus into transmit mode, send START condition, send slave address (with R/W = 0), then send address of first register to read. – Put IIC bus into transmit mode, send START condition, send slave address (with R/W = 1), switch to receive mode, read dummy byte from IBRD to start IIC clock, then receive data. • Need function iic_swrcv() to switch from transmit to receive mode, and read dummy byte from IBCR. • When receiving multiple bytes from slave, need to send NACK after last byte in order to tell slave to release bus. – If you don’t do this, slave will hold onto bus, and you cannot take over bus for next operation • Look at the flow chart from Page 39 of the IIC manual (next page) to see what to do • I have three receive functions: 1. iic_receive(): Used for receiving all but last two bytes – Waits for IBIF flag to set, indicating new data – Clears IBIF after it has been set – Reads data from IBDR, which starts next read 2. iic_receive_m1(): Used for receiving next to last byte – Waits for IBIF flag to set, indicating new data – Clears IBIF after it has been set – Sets TXAK bit so there will be no ACK sent on reading the last byte – Reads data from IBDR, which starts next read 3. iic_receive_last(): Used for receiving last byte – Waits for IBIF flag to set, indicating new data – Clears IBIF after it has been set – Clears TXAK bit so ACK is re-enabled – Clears MS/SL bit to generate a STOP bit after this transfer is complete – Sets Tx/Rx bit so MC9S12 will not start SCLK to receive another byte after reading from IBDR. – Reads data from IBDREE 308 Spring 2011EE 308 Spring 2011 Asynchronous Data Transfer • In asynchronous data transfer, there is no clock line between the two devices • Both devices use internal clocks with the same frequency • Both devices agree on how many data bits are in one data transfer (usually 8, sometimes 9) • A device sends data over an TxD line, and receives data over an RxD line – The transmitting device transmits a special bit (the start bit) to indicate the start of a transfer – The transmitting device sends the requisite number of data bits – The transmitting device ends the data transfer with a special bit (the stop bit) • The start bit and the stop bit are used to synchronize the data transferEE 308 Spring 2011 Asynchronous Data Transfer • The receiver knows when new data is coming by looking for the start bit (digital 0 on the RxD line). • After receiving the start bit, the receiver looks for 8 data bits, followed by a stop bit (digital high on the RxD line). • If the receiver does not see a stop bit at the correct time, it sets the Framing Error bit in the status register. • Transmitter and receiver use the same internal clock rate, called the Baud Rate. • At 9600 baud (the speed used by D-Bug12), it takes 1/9600 second for one bit, 10/9600 second, or 1.04 ms, for one byte. Asynchronous Serial ProtocolsEE 308 Spring 2011 Asynchronous Serial Protocols • The SCI interface on the MC9S12 uses voltage levels of 0 V and +5 V. The RS-232 standard uses voltage levels of +12 V and -12 V. – The Dragon12-Plus board uses a Maxim MAX232A chip to shift the TTL levels from the MC9S12 to the RS-232 levels necessary for connecting to a standard serial port. 0 V from the SCI is converted to +12 V on the DB-9 connector and +5 V from the SCI is converted to -12 V on the DB-9 connector. – The RS-232 standard can work on cables up to a length of 50 feet. • Another asynchronous standard is RS-485. Dragon12-Plus board can use SCI1 in RS- 485 mode – RS-485 is a two-wire differential asynchronous protocol – Multiple devices can connect to the same two wires – Only one device on the RS-485 bus can transmit; all the other devices are in receive mode – The Dragon12-Plus DS75176 differential-to-single ended converter to convert the single-ended SCI1 data to differential RS-485 data – Bit 0 of Port J determines if the RS-485 should be in receive mode or transmit mode – RS-485 can work with cables up to a length of 1,000 feet.EE 308 Spring 2011 Parity in Asynchronous Serial Transfers • The HCS12 can use a parity bit for error detection. – When enabled in SCI0CR1, the parity function uses the most significant bit for parity. – There are two types of parity – even parity and odd parity * With even parity, and even number of ones in the data clears the parity bit; an odd number of ones sets the parity bit. The data transmitted will always have an even number of ones. * With odd parity, and odd number of ones in the data clears the parity bit; an even number of ones sets the parity bit. The
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