Revision HistoryTable of ContentsList of FiguresList of TablesSection 1 Introduction1.1 Overview1.2 Features1.3 Modes of Operation1.4 Block DiagramSection 2 PWM8b8cSignal Description2.1 Overview2.2 Detailed Signal Descriptions2.2.1 PWM7 — PWM8b8c Channel 72.2.2 PWM6 — PWM8b8c Channel 62.2.3 PWM5 — PWM8b8c Channel 52.2.4 PWM4 — PWM8b8c Channel 42.2.5 PWM3 — PWM8b8c Channel 32.2.6 PWM2 — PWM8b8c Channel 22.2.7 PWM1 — PWM8b8c Channel 12.2.8 PWM0 — PWM8b8c Channel 0Section 3 Memory Map and Register Definition3.1 Overview3.2 Module Memory Map3.3 Register Descriptions3.3.1 PWM Enable Register (PWME)3.3.2 PWM Polarity Register (PWMPOL)3.3.3 PWM Clock Select Register (PWMCLK)3.3.4 PWM Prescale Clock Select Register (PWMPRCLK)3.3.5 PWM Center Align Enable Register (PWMCAE)3.3.6 PWM Control Register (PWMCTL)3.3.7 Reserved Register (PWMTST)3.3.8 Reserved Register (PWMPRSC)3.3.9 PWM Scale A Register (PWMSCLA)3.3.10 PWM Scale B Register (PWMSCLB)3.3.11 Reserved Registers (PWMSCNTx)3.3.12 PWM Channel Counter Registers (PWMCNTx)3.3.13 PWM Channel Period Registers (PWMPERx)3.3.14 PWM Channel Duty Registers (PWMDTYx)3.3.15 PWM Shutdown Register (PWMSDN)Section 4 Functional Description4.1 PWM Clock Select4.1.1 Prescale4.1.2 Clock Scale4.1.3 Clock Select4.2 PWM Channel Timers4.2.1 PWM Enable4.2.2 PWM Polarity4.2.3 PWM Period and Duty4.2.4 PWM Timer Counters4.2.5 Left Aligned Outputs4.2.6 Center Aligned Outputs4.2.7 PWM 16-Bit Functions4.2.8 PWM Boundary CasesSection 5 Resets5.1 GeneralSection 6 Interrupts6.1 Interrupt OperationUser Guide End SheetMotorola reserves the right to make changes without further notice to any products herein to improve reliability, function ordesign. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,or authorized for use as components in systems intended for surgical implant into the body, or other applications intended tosupport or sustain life, or for any other application in which the failure of the Motorola product could create a situation wherepersonal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorizedapplication, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmlessagainst all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim ofpersonal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola wasnegligent regarding the design or manufacture of the part.DOCUMENT NUMBERS12PWM8B8CV1/D1 PWM_8B8CBlock User GuideV01.17OriginalReleaseDate:12MAR1998Revised: 1 Aug 2004Motorola Inc.PWM_8B8C Block User Guide V01.172Revision HistoryVersionNumberRevisionDateEffectiveDateAuthor Description of Changes00.00 3-12-98 First pass release00.01 3-15-98- Updates of Section 1 based on Nancy Thomas peer review andinternal spec review.- Added initial information into Section 2.00.02 4-7-98- Updates of Section 1 and Section 2 per MSIL review.- Updated cover page per latest spec template review.01.00 4-15-98- Updated per Rev. 3.0 TSCS Module Spec Template.- Changed the Port and DDR register names to match the latestHCS12 naming convention.- Added the reset state under each counter, period, and dutyregister in the Register Description sections.- Added Design for Testability sub-section in Section 2 to describescan implementation.- Updated Module I/O signal names in Section 2 per the latestHCS12 signal naming convention.- Frozen PWM spec sent to Delco.01.01 4-30-98- Added Document Number (12MRE31052W) to cover page ofspec per QS9000 requirements.- Changed PWMEN register to PWME and also changed the bitnames from PWENx to PWMEx to follow the enable namingconvention.- Changed PWMCEN register to PWMCAE and also changed thebit names from CENx to CAEx to avoid having the same registername as the PWMC module.- Section 2 Module I/O list changed to have only 1 input bufferenable signal (pwm_ibe_t4) for the entire port. The reset signalname was also changed to vsc_reset_t4 per the latest busdefinition document.- Added further clarification on DISCRW test bit in Section 2. If set,duty and period registers are not loaded with the buffer value.01.02 5-14-98- Updated per Rev. 3.1, 3.2 and 3.3 TSCS Module Spec Template.- Removed Table 1-1 PWM Register Address Summary. Added theAddress Offset along side the registers in Figure 1-2 PWM RegisterMap.- Added WARNING regarding writing to the test registers in specialmodes.- Added footnote regarding the counter value in the Period=0boundary case.- Removed “weasel” words--may and should.PWM_8B8C Block User Guide V01.17301.03 5-27-98Summary of changes:- Added clarification on how the counter counts in left and centeraligned output modes.- Added further clarification on the Period=0 boundary case. Addedthat the counter=$00.- Added further clarification on what occurs on writes to thecounter--output is changed according to the polarity bit.- Added Caution regarding the first PWM cycle after the channel isenabled can be irregular.- Replaced bit ‘RDP’ with ‘RDPPWM’ and bit ‘PUPP’ with‘PUPPWME’ to match port control bit naming conventions.- Added ‘iam8bit’ signal in Table 2-1.- Added Table 2-2, Engineering Electrical Specs.- Added statement in Section 2 regarding DISCRW bit in PWMTSTregister. When bit is set, the output is not changed according to thepolarity bit.- Added statement in Section 2 regarding DISCRM bit in PWMTSTregister. When bit is set, the duty and period registers do not getloaded with the buffer value.- Corrected left and center aligned max PWM output frequencies inTable A-2.- Created Table A-3 for the PWM Period/Duty ResolutionCharacteristics.- Miscellaneous clean up.01.04 7-1-98* Changed reset state of PWMPERx and PWMDTYx registers toFF.* In section 2: changed some bus interface signal names: vsc_wait_t2 changed to vsc_wait_t3 vsc_bdmact_t2 changed to vsc_bdmact_t4 vsc_smod_t2 changed to vsc_smod_t4* In section 2: Added a note that in concatenated, left aligned, DISCRW=1writing 16 bit (high-byte-data, low-byte-data) to the counter causesthe high byte of the counter to start counting from (high-byte-data)and the low byte of the counter to start counting from
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