EE 308 Spring 2010Summary of MC9S12 addressing modesX + 300A6 2DREL Relative BRA $1050 20 23LBRA $1F00 18 20 0E CFPC + 2 + OffsetPC + 4 + OffsetX−3 (X−3 −> X)X + 30Extended 0x0935EXT LDAA $2035 B6 20 35INH InherentIMM ImmediateDIR DirectNameIndexedABALDAA $35 0x0035PC + 1NoneLDAA #$35Example Op CodeEffectiveAddressLDAA 3,X X + 3ADDRESSING MODESIDXIDX1IDX2IDX IndexedIDX IndexedIDX IndexedIDX IndexedPostincrementPreincrementLDAA 3,X+ X (X+3 −> X)LDAA 3,+X X+3 (X+3 −> X)PostdecrementPredecrementLDAA 3,X−LDAA 3,−XX (X−3 −> X)LDAA 30,XLDAA 300,X A6 E2 01 2CA6 03A6 E0 1396 3586 3518 06A6 32A6 22A6 3DA few instructions have two effective addresses:• MOVB #$AA,$1C00 Move byte 0xAA (IMM) to address $1C00 (EXT)• MOVW 0,X,0,Y Move word from address pointed to by X (IDX) to address pointedto by Y (IDX)A few instructions have three effective addresses:• BRSET FOO,#$03,LABEL Branch to LABEL (REL) if bits #$03 (IMM) of variableFOO (EXT) are set.1EE 308 Spring 2010Using X and Y as Pointers• Registers X and Y are often used to point to data.• To initialize pointer useldx #tablenotldx table• For example, the following loads the address of table ($1000) into X; i.e., X will pointto table:ldx #table ; Address of table => XThe following puts the first two bytes of table ($0C7A) into X. X will not point totable:ldx table ; First two bytes of table => X• To step through table, need to increment pointer after useldaa 0,xinxorldaa 1,x+table: dc.b 12,122,−43,0 org $900 dc.b ’a’,’b’,’c’,’d’7A006162630CD564table2EE 308 Spring 2010Which branch instruction should you use?Branch if A > BIs 0xFF > 0x00?If unsigned, 0xFF = 255 and 0x00 = 0, so 0xFF > 0x00 so 0xFF < 0x00If signed, 0xFF = −1 and 0x00 = 0,Using unsigned numbers: BHI (checks C bit of CCR)For unsigned numbers, use branch instructions which check C bitFor signed numbers, use branch instructions which check V bitUsing signed numbers: BGT (checks V bit of CCR)3EE 308 Spring 2010Hand Assembling a ProgramTo hand-assemble a program, do the following:1. Start with the org statement, which shows where the first byte of the program will gointo memory.(E.g., org $2000 will put the first instruction at address $2000.)2. Look at the first instruction. Determine the addressing mode used.(E.g., ldab #10 uses IMM mode.)3. Look up the instruction in the MC9S12 S12CPUV2 Reference Manual, find theappropriate Addressing Mode, and the Object Code for that addressing mode.(E.g., ldab IMM has object code C6 ii.)• Table A-1 of the S12CPUV2 Reference Manual has a concise summary of theinstructions,addressing modes, op-codes, and cycles.4. Put in the object code for the instruction, and put in the appropriate operand. Becareful to convert decimal operands to hex operands if necessary.(E.g., ldab #10 becomes C6 0A.)5. Add the number of bytes of this instruction to the address of the instruction to deter-mine the address of the next instruction.(E.g., $2000 + 2 = $2002 will be the starting addrss of the next instruction.)org $2000ldab #10loop: clradbne b,loopswi4EE 308 Spring 2010S12CPUV2 Reference Manual, Rev. 4.0Freescale Semiconductor 387LBGT rel16 Long Branch if Greater Than(if Z + (N ⊕ V) = 0) (signed)REL 18 2E qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LBHI rel16 Long Branch if Higher(if C + Z = 0) (unsigned)REL 18 22 qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LBHS rel16 Long Branch if Higher or Same(if C = 0) (unsigned)same function as LBCCREL 18 24 qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LBLErel16 Long Branch if Less Than or Equal(if Z + (N ⊕ V) = 1) (signed)REL 18 2F qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LBLO rel16 Long Branch if Lower(if C = 1) (unsigned)same function as LBCSREL 18 25 qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LBLSrel16 Long Branch if Lower or Same(if C + Z = 1) (unsigned)REL 18 23 qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LBLT rel16 Long Branch if Less Than(if N ⊕ V = 1) (signed)REL 18 2D qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LBMI rel16 Long Branch if Minus (if N = 1) REL 18 2B qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LBNErel16 Long Branch if Not Equal (if Z = 0) REL 18 26 qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LBPLrel16 Long Branch if Plus (if N = 0) REL 18 2A qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LBRArel16 Long Branch Always (if 1=1) REL 18 20 qq rrOPPP OPPP– – – – – – – –LBRNrel16 Long Branch Never (if 1 = 0) REL 18 21 qq rrOPO OPO– – – – – – – –LBVCrel16 Long Branch if Overflow Bit Clear (if V=0) REL 18 28 qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LBVSrel16 Long Branch if Overflow Bit Set (if V = 1) REL 18 29 qq rrOPPP/OPO1OPPP/OPO1– – – – – – – –LDAA #opr8iLDAA opr8aLDAA opr16aLDAA oprx0_xyspLDAA oprx9,xyspLDAA oprx16,xyspLDAA [D,xysp]LDAA [oprx16,xysp](M) ⇒ ALoad Accumulator AIMMDIREXTIDXIDX1IDX2[D,IDX][IDX2]86 ii96 ddB6 hh llA6 xbA6 xb ffA6 xb ee ffA6 xbA6 xb ee ffPrPfrPOrPfrPOfrPPfIfrPffIPrPfPrfPrOPrfPrPOfrPPfIfrfPfIPrfP– – – – ∆ ∆ 0 –LDAB #opr8iLDAB opr8aLDAB opr16aLDAB oprx0_xyspLDAB oprx9,xyspLDAB oprx16,xyspLDAB [D,xysp]LDAB [oprx16,xysp](M) ⇒ BLoad Accumulator BIMMDIREXTIDXIDX1IDX2[D,IDX][IDX2]C6 iiD6 ddF6 hh llE6 xbE6 xb ffE6 xb ee ffE6 xbE6 xb ee ffPrPfrPOrPfrPOfrPPfIfrPffIPrPfPrfPrOPrfPrPOfrPPfIfrfPfIPrfP– – – – ∆ ∆ 0 –LDD #opr16iLDD opr8aLDD opr16aLDD oprx0_xyspLDD oprx9,xyspLDD oprx16,xyspLDD [D,xysp]LDD [oprx16,xysp](M:M+1) ⇒ A:BLoad Double Accumulator D (A:B)IMMDIREXTIDXIDX1IDX2[D,IDX][IDX2]CC jj kkDC ddFC hh llEC xbEC xb ffEC xb ee ffEC xbEC xb ee ffPORPfRPORPfRPOfRPPfIfRPffIPRPfOPRfPROPRfPRPOfRPPfIfRfPfIPRfP– – – – ∆ ∆ 0 –Note 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.LDS #opr16iLDS opr8aLDS opr16aLDS oprx0_xyspLDS oprx9,xyspLDS oprx16,xyspLDS [D,xysp]LDS [oprx16,xysp](M:M+1) ⇒ SPLoad Stack PointerIMMDIREXTIDXIDX1IDX2[D,IDX][IDX2]CF jj kkDF ddFF hh llEF xbEF xb ffEF xb ee ffEF xbEF xb ee ffPORPfRPORPfRPOfRPPfIfRPffIPRPfOPRfPROPRfPRPOfRPPfIfRfPfIPRfP– – – – ∆ ∆ 0 –LDX #opr16iLDX opr8aLDX opr16aLDX oprx0_xyspLDX oprx9,xyspLDX oprx16,xyspLDX [D,xysp]LDX [oprx16,xysp](M:M+1) ⇒ XLoad Index Register XIMMDIREXTIDXIDX1IDX2[D,IDX][IDX2]CE jj kkDE ddFE hh llEE xbEE xb
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