Revision HistoryTable of ContentsList of FiguresList of TablesSection 1 Introduction1.1 Overview1.2 Features1.3 Modes of Operation1.4 Block DiagramSection 2 Signal Description2.1 Overview2.2 Detailed Signal Descriptions2.2.1 VDDPLL, VSSPLL2.2.2 XFC2.2.3 EXTAL, XTAL2.2.4 RESET2.2.5 XCLKSSection 3 Memory Map and Registers3.1 Overview3.2 Module Memory Map3.3 Register Descriptions3.3.1 CRG Synthesizer Register (SYNR)3.3.2 CRG Reference Divider Register (REFDV)3.3.3 Reserved Register (CTFLG)3.3.4 CRG Flags Register (CRGFLG)3.3.5 CRG Interrupt Enable Register (CRGINT)3.3.6 CRG Clock Select Register (CLKSEL)3.3.7 CRG PLL Control Register (PLLCTL)3.3.8 CRG RTI Control Register (RTICTL)3.3.9 CRG COP Control Register (COPCTL)3.3.10 Reserved Register (FORBYP)3.3.11 Reserved Register (CTCTL)3.3.12 CRG COP Timer Arm/Reset Register (ARMCOP)Section 4 Functional Description4.1 General4.2 Functional Blocks4.2.1 Oscillator (OSC)4.2.2 Phase Locked Loop (PLL)4.2.2.1 PLL Operation4.2.2.2 Acquisition and Tracking Modes4.2.3 System Clocks Generator4.2.3.1 External clock mode4.2.4 Clock Monitor (CM)4.2.5 Clock Quality Checker4.2.6 Computer Operating Properly Watchdog (COP)4.2.7 Real Time Interrupt (RTI)4.3 Operation Modes4.3.1 Normal Mode4.3.2 Self Clock Mode4.4 Low Power Options4.4.1 Run Mode4.4.2 Wait Mode4.4.3 CPU Stop Mode4.4.3.1 Wake-up from Pseudo-Stop (PSTP=1)4.4.3.2 Wake-up from Full Stop (PSTP=0)Section 5 Resets5.1 General5.2 Description of Reset Operation5.2.1 Clock Monitor Reset5.2.2 Computer Operating Properly Watchdog (COP) Reset5.2.3 Power-On ResetSection 6 Interrupts6.1 General6.2 Description of Interrupt Operation6.2.1 Real Time Interrupt6.2.2 PLL Lock Interrupt6.2.3 Self Clock Mode InterruptMotorola reserves the right to make changes without further notice to any products herein to improve reliability, function ordesign. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,or authorized for use as components in systems intended for surgical implant into the body, or other applications intended tosupport or sustain life, or for any other application in which the failure of the Motorola product could create a situation wherepersonal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorizedapplication, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmlessagainst all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim ofpersonal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola wasnegligent regarding the design or manufacture of the part.DOCUMENT NUMBERS12CRGV2/D1CRGBlock User GuideV02.07Original Release Date: 29 FEB 2000Revised: 11 Mar 2002SPS, TSPG, 8/16 BitMotorola, Inc Freescale Semiconductor, I Freescale Semiconductor, Inc.For More Information On This Product, Go to: www.freescale.comnc...CRG Block User Guide — V02.072Revision HistoryVersionNumberRevisionDateEffectiveDateAuthor Description of ChangesV02.00 11/09/00 10/18/00 Initial SRS2.0 compliant releaseV02.01 03/03/01 03/03/01 Added RSBCK bit.V02.02 03/22/01 Make the content SRS compliant (usable as a customer document)V02.03 13 July 01 Minor correctionsV02.04 27 July 01 27 July 01Enhanced Block diagram (VREG, POR), Corrected register figureCRGINT to read and writeV02.05 15 Oct 01 15 Oct 01 Replaced by HCS12V02.06 21 Dec 01 21 Dec 01Corrected CDC in Colpitts Oscillator Connections diagram.V02.07 11 Mar 02 11 Mar 02Removed document number from all pages execept cover pageReplaced fVCOMIN by fSCM Freescale Semiconductor, I Freescale Semiconductor, Inc.For More Information On This Product, Go to: www.freescale.comnc...CRG Block User Guide — V02.073Table of ContentsSection 1 Introduction1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Section 2 Signal Description2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132.2 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132.2.1 VDDPLL, VSSPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132.2.2 XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132.2.3 EXTAL, XTAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132.2.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142.2.5 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Section 3 Memory Map and Registers3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . …
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