EE 308 Spring 2010MICROPROCESSORMEMORYPRINCETON (VON NEUMAN) ARCHITECTURESTATUSOUTINCONTROLCLOCKCONTROLALUDATAINSTRUCTION& ADDRCONTROL1EE 308 Spring 2010InstAddr_Mux_SelALU_CtrlZ_LoadC_LoadV_LoadA_LoadX_LoadControlPC_LoadPC_IncNVCZN_LoadMem_WALUZAddr_MuxAXPCMARIRVCAddressNMemoryData_MuxData_Mux_SelProcessor0xFF Reset VectorInputOutputIR_LoadMAR_Load2EE 308 Spring 2010MEMORYADDR(N Bits)DATA(M Bits)CONTROLCOMPUTERComputer with N bit address bus can access Control lines tell memory when computer wantsN2 bytes of dataComputer with M bit data bus can accessM bits of data in one memory cycleto read (write) data, and if access is read or writelocation computer wants to read (write)Value on address bus tells memory which3EE 308 Spring 2010Address, Data and Control Buses• A microprocessor system uses address, data and control buses to communicate withexternal memory and memory-mapped peripherals• The address bus determines which memory location to access• The control bus specifies whether the memory cycle is a read (into microprocessor) ora write (out of microprocessor) cycle, and specifies timing information for the cycle• The data bus contains the data being transfered during the memory cycle• For example, consider the following simple MC9S12 program, which continuously in-crements the contents of address 0x0400:org 0x2000loop: inc 0x0400bra loop– The program is stored in memory starting at memory location 0x2000– The MC9S12 Program Counter starts at address 0x2000– The MC9S12 reads the first instruction, inc 0x0400, located in address 0x2000through 0x2002– The MC9S12 then reads the contents of memory location 0x0400, takes an internalmemory cycle to increment the value, then writes the new value out to address0x0400– The MC9S12 then reads the next instruction, bra 0x2000– The MC9S12 takes one memroy cycle to load the program counter with the newvalue of 0x2000, and to clear its internal pipeline, then reads the instruction at0x2000 to figure out what to do next4EE 308 Spring 2010The MC9S12 address, data and control buses (simplified)• Note: The following diagram assumes that the MC9S12 accesses one byte at a time• The MC9S12 actually accesses two bytes (16 bits) at a time, when it can• What actually occurs on the MC9S12 bus is a little more complicated than what is shown below2004: FB2001: 042000: 722002: 002003: 20ADDRDATAR/W2000 2001 2002 FFFF 2003 2004A3 00 A4 20 FB .org 0x2000 bra loop2000FFFF0072 00 72loop: inc 0x0400040400 0400 bra 0x2000inc 0x0400MC9S12 ADDRESS, DATA AND CONTROL BUS (SIMPLIFIED)5EE 308 Spring 2010LSTRB (together with ADDR0) tells memory if MC9S12 is accessing one or two bytesADDR(16)ER/WDATA(16)LSTRB1024 bytes = 1 kB65536 bytes = 64 kBat a timeFor example, the instruction LDX $0900will read the two bytes at address $0900 and $0901R/W high => readR/W low => write synchronizes data accessesSometimes MC9S12 only accesses one byte −− e.g., LDAA $0900 The MC9S12 accesses only the byte at address $0900E tells memory when MC9S12 is reading (writing) −−MC9S12MC9S12 has 16 bit address bus − can access 65536 bytesMC9S12 has 16 bit data bus − can access 16 bits (2 bytes)MEMORYorPERIPHERALR/W tells memory (or peripheral) if MC9S12 is reading or writing6EE 308 Spring 2010The MC9S12 Memory Map• The MC9S12 has address regions occupied by internal memory and peripherals• A diagram showing which address regions are used is called a memory map• Here is a memory map of the MC9S12DP256 with no added memory or peripherals0x00000x03FF0x04000x0FFF0x10000x3BFF0x3C000x3FFF0x40000x7FFF0x80000xBFFF0xC0000xFFFFEEPROMEEPROMEEPROMFlashFlashFlashD−Bug 12RAMRAMRegistersUserEEPROMBankedD−Bug 123 KB1 KB16 KB1 KB11 KB16 KB16 KB7EE 308 Spring 2010The Expanded MC9S12 Memory Map• We will add external peripherals to the MC9S12• First, we will disable the Flash EEPROM at address 0x4000 through 0x7FFF (whichwe are not using anyway)• Here is a memory map of the MC9S12DP256 with the peripherals we will add• The peripherals will be put at 0x4000 and 0x4001for external peripherals0x00000x03FF0x04000x0FFF0x10000x3BFF0x3C000x3FFF0x40000x7FFF0x80000xBFFF0xC0000xFFFFEEPROMEEPROMFlashFlashD−Bug 12RAMRAMRegistersUserEEPROMBankedD−Bug 123 KB1 KB1 KB11 KB16 KB16 KBSpaceUnusedUse address 0x4000 − 0x40018EE 308 Spring 2010Simplified MC9S12 Write C ycle• When the MC9S12 writes data to memory it does the following:– It puts the address it wants to write to on the address bus (when E-clock goeslow)– It puts the data it wants to write onto the data bus– It brings the Read/Write (R/W) line low to indicate a write– The MC9S12 expects the external device at the given address will latch the datainto its registers data on the falling edge of the E-clockWRITE: MC9S12 puts address on address busADDR(16)R/WMEMORY Memory latches data on falling edge of E clockER/WADDRDATA0xfedcDATA(16)Example: Write 0xfedc to address 0x3456 & 34570x3456ELSTRB puts data on data bus brings R/W lowMC9S129EE 308 Spring 2010Simplified MC9S12 Read Cycle• When the MC9S12 reads data from memory it does the following:– It puts the address it wants to read from on the address bus (when E-clock goeslow)– It brings the Read/Write (R/W) line high to indicate a read– The MC9S12 expects the external device at the given address will put data on thedata bus– On the falling edge of the E-clock, the MC9S12 latches the data into its internalregisterlREAD: MC9S12 puts address on address busMC9S12ADDR(16)MEMORYER/WADDRDATA Memory puts data on data bus HC12 latches data on falling edge of E clockExample: Read from address 0x5678 & 0x56790x56780xba98DATA(16)R/WELSTRB brings R/W high 10EE 308 Spring 2010The Real MC9S12DP256 Bus• Up to now we have bee n using the M C9S12 in Single Chip Mode– In Single Chip Mode the MC9S12 does not have an external address/data bus• The MC9S12 can be run in Expanded Mode– In Expanded Mode the MC9S12 does have an external address/data bus• Things are a little more complicated on the real MC9S12DP256 bus than shown in thesimplified diagrams above• The MC9S12DP256 has a multiplexed address/data bus• The MC9S12DP256 sometimes accesses a single byte on a memory cycle, and it some-times access two bytes on a memory cycleThe Multiplexed Address/Data Bus• The MC9S12DP256 has a limited number of pins it can use• To have full 16-bit address bus and
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