University of Toronto ECE532 Digital Hardware Lab 5 Adding a User Designed Peripheral Version 1 5 8 16 2004 This lab can be started during Lab 4 and completed during Lab 5 if necessary Goals Add a user designed peripheral to a basic MicroBlaze system Demonstrate the required structure necessary for interfacing user designed cores to the Xilinx cores Learn about how you would make your own core to attach to the OPB Requirements Module 1 Lab 1 Building a base system Preferably do Modules 1 4 Preparation 1 Review the handout outlining the EDK project structure provided in Lab 1 We will be focusing on the pcores subdirectory for this lab 2 Read the document Integrating a Verilog design into a MicroBlaze System Much of the content is also applicable to creating VHDL cores Pay particular attention to the section about Adding the design to a MicroBlaze system 3 If you are unfamiliar with the profiling of code read the manual page for gprof which is available on the ugsparcs with the man command Background To this point you have only been adding cores from the existing library If you cannot find a core with the required functionality you will have to add your own This lab adds a simple core that can be used to profile the code running on a MicroBlaze This has similar functionality to the gprof utility for profiling that is available in the GNU tools However it is much more accurate You may find it useful for your project 1 University of Toronto ECE532 Digital Hardware Lab 5 Adding a User Designed Peripheral Step by step 1 Copy your working lab1 project into a new directory 2 Add a pcores subdirectory to your new project directory Using an ssh window login to your ugsparc account The files you will need for this lab can be found in pc courses 532 labs User Area lab4 5 Copy 1 system c to the code directory of your project 2 the snoopy v1 00 a directory into the pcores directory and 3 the sst script and example results txt to the root of the project directory 4 the OPBInterfaceModule directories to a directory where you can refer to it later Note You may find the cp r command useful 3 Take time to look through the directory structure of the snoopy core The naming structure is essential for XPS to be able to detect a user s peripheral All user cores must be located in the pcores subdirectory or in a globally specified path to a peripheral repository User cores can be defined using either VHDL or Verilog but the tools do not support simulation of mixed designs Therefore it may be preferable to write the designs in VHDL Along with the hdl files used to implement the core the user must also include data files a pao file Peripheral Analyze Order and an mpd file Microprocessor Peripheral Description The pao file lists the order in which files in your design should be synthesized to resolve component architectures The mpd file describes the external interface of the core to a system For more information on these files and their structure go to the Embedded System Tools Guide Notice that the version numbers in the core name and the version numbers in the data file names differ The version in the core name is the core s version The version in the data file names is the version of the syntax used to write the data file The easiest method for including user IP into an EDK project is to follow an example When you develop your own cores for your project you can use snoopy as a guide The cores provided by Xilinx in the EDK6 2 hw XilinxProcessorIPLib pcores may also be used as a reference There is also a document describing how to add user cores to Embedded Systems the User Core Template Reference Guide but it is meant for relatively complex cores providing the user an IP Interface IPIF to simplify user core connections to system buses 4 The snoopy core is a snooping profiler that is able to profile software running on a softcore processor in real time The counters calculate the exact number of clock cycles spent executing contiguous address ranges The user specifies the number of counters and the lower and upper bounds for 2 University of Toronto ECE532 Digital Hardware Lab 5 Adding a User Designed Peripheral each counter before synthesis This information can be used by embedded system designers to determine which if any sections of the software should be moved to hardware to achieve the required design specifications 5 Open the Add Edit cores menu The snoopy core should appear in the list of peripherals you can add to your design Add the snoopy core and connect it to the slave opb bus The core requires 0x100 bytes and a 0x100 byte alignment Since the tools resolve connections to the opb and lmb buses based on the address of a peripheral we suggest address range 0xffffff00 to 0xffffffff to guarantee the peripheral resides on the opb 6 For the snoopy core to work it must be interfaced with the system clock and the PC EX and valid instr ports on the Microblaze core Connect the clock from the snoopy core OPB Clk to the system clock Don t forget to check the net name and the scope under the Ports tab Unfortunately the PC EX and valid instr ports on the snoopy core are not visible through the Add Edit core interface Therefore they will have to be added manually to the hardware description 7 Close the XPS GUI Go to your project directory and open the system mhs file You are going to edit this file by hand It is important to remember that this file contains the project description used by XPS to generate your MicroBlaze system Therefore it is safest to only edit the mhs file when XPS is not running 8 You are going to add two lines of code to the MicroBlaze and snoopy module descriptions Each module description begins with a BEGIN module type Look for the MicroBlaze core and the snoopy core and add the following two lines just before both END statements PORT PC EX PC EX PORT valid instr valid instr 9 Save and close the mhs file Reopen XPS and your current project Go to the Add Edit cores menu If you look under the ports tab you should now see that the valid instr and PC EX ports of the processor have been connected to snoopy 10 The core lets you set a reset address for clearing the counters the number of counters you want to use maximum of 16 and the upper and lower bounds for the instruction addresses Choose an address that is within the address range assigned to the core Hints if you used the suggested address range for the core the default reset address 0xffffffe4 will be fine Remember this is found under