ECE 532 Digital Hardware Final Project Group Report Photoshop Functionalities on FPGA Group Pearl Liu 990975307 George Ng 990857355 Date March 28 2005 Table of Contents System Design Overview 1 Goals 1 Original Design 1 Final Design 1 Block diagram 2 Description of IP Blocks 3 Outcome 5 Description of the Blocks 6 Custom Designed Blocks 6 CoreGen Blocks 10 Xilinx SVGA Controller and ZBT RAM Controller Blocks 10 Testbenches and Models 12 Description of the Design Tree 13 Instructions to run the system 16 Instructions to run the Matlab and Verilog Testbench 17 References 18 System Design Overview Goals The goal of the project was to implement a real time video capture Photoshop digital filter processing and display system on FPGA The implementation platform is the Virtex II XC2V2000 FF896 Speed Grade 4 Development Board Original Design The original design was to use a video capture core that would continuously capture video data from a digital camera to ZBT RAM The captured image would then be processed by a Photoshop type of digital filter implemented in HDL code The filtered image would then be displayed on a VGA monitor using a VGA display controller The entire process would be performed in real time Final Design All parts of the proposed project were implemented except for the real time video capture component This decision was taken to simplify our project Instead of capturing the image in real time an image was loaded from a separate project into the ZBT RAM A 32 bit flipped row order bitmap image file format was used From our research we found that the pixel RGB red green and blue components in a bitmap are stored directly in consecutive bytes where each byte represents the pixel color To simplify the design of the memory controller we decide to use a 32 bit bitmap file format over a 24 bit bitmap format the 32 bit bitmap file format uses 24 bits to store the color data and pads the remaining 8 bits This was done since the ZBT RAM reads out 32 bits at a time In the case of 24 bit bitmaps the RGB components of a pixel can potentially straddle a 32 bit boundary as result multiple reads may be needed performed to retrieve a single pixel thus complicating the memory controller design The way our design works is that once there is image data in the ZBT RAM it will immediately send the data to the digital filter within the FPGA The filtered data is then passed on to a 32 bit x 32 deep FIFO using a custom designed ZBT memory to FIFO controller Once the FIFO becomes full a FIFO to display controller is used to transfer the filtered data out of the FIFO and to the SVGA display controller The SVGA controller provided by Xilinx handled the reads and writes from a ZBT video memory bank within the display block and the filtered image would be immediately displayed on the monitor 1 Block diagram Digital Photoshop Filter and Display Blocks 2 Bitmap image loader Bitmap image loader is the direct implementation of lab m08 It is used to initially load image data into a ZBT RAM bank 0 No further description is provided Lab m08 can be found at http www eecg toronto edu pc courses edk modules 6 3 m08 pdf Description of IP Blocks IP Block Custom Blocks displaypattern v mem2fifo ctrl v Functionality Top level hardware block which connects the FIFO ZBT controllers and custom controllers Takes image data from ZBT RAM and inputs it through the filter and into the FIFO Origin Custom design by George and Pearl Custom Design by George 3 fifo2disp ctrl v Takes image data from the FIFO and inputs it into display controller gblur v Low pass filter code that blurs an image emboss v High pass filter code that embosses an image Xilinx Display Controller and ZBT RAM Controller ADDR BUS INTERFACE v Address bus interface for ZBT RAM controller BM MODE SVGA CTRL v SVGA controller CTRL BUS INTERFACE v Control bus interface for the ZBT RAM controller DATA BUS INTERFACE v Data bus interface for the ZBT RAM controller DRIVE DAC DATA v Directs data to SVGA MEMORY CTRL v Memory controller module of ZBT RAM PIPELINES v Provides pipelines for data WRITES and a latch for the data READS in ZBT SVGA TIMING GENERATION v Generates timing and control signal for DAC VGA output connector ZBT CONTROL v ZBT RAM controller top level interface Xilinx CoreGen mem fifo v CoreGen FIFO wrapper which is used as a buffer to store filtered data and send to ZBT RAM of display controller Custom Design by George Custom Design by Pearl Custom Design by Pearl Xilinx SVGA IP Xilinx SVGA IP modified by connecting the RAM and SVGA controller to the same pixel clock Xilinx SVGA IP Xilinx SVGA IP Xilinx SVGA IP Xilinx SVGA IP Xilinx SVGA IP Xilinx SVGA IP Xilinx SVGA IP Instantiated from CoreGen 4 Outcome How Well It Works Once a bitmap image was loaded into the ZBT RAM with the use of an external image loader we were able to blur a bitmap image and display the resulting effect on the VGA monitor We discovered that the VGA color output of the Xilinx board was not accurate All colors suffered from a tinge of green especially the color black We suspect that this problem might be related to the DAC on the board Although the primary colors of red green and blue were displayed accurately more complex 24 bit colors were not displayed accurately To prove that we had not connected the color components incorrectly to the display controller we created a bitmap with the reference RGB colors as well as more complex 24 bit colors on the same bitmap for display When the bitmap was displayed on the monitor the RGB colors displayed correctly while other more complicated colors were not Suggestion for Further Work or Improvement Although a blur and an emboss Photoshop filter were created they were both implemented in different projects which meant the user was unable to select the filter of choice without reprogramming the FGPA A C program was written to interface with the FSL to enable the user to select which Photoshop effect to be done on the bitmap image but due to time constraint the FSL was not integrated with the rest of the system Thus further work would be to integrate the FSL with the final design to allow filter selections Real time image capture would enhance the coolness of the project Due to time constraints in figuring out the display controller and ZBT RAM controllers there was not sufficient time to investigate integration of a video capture core More advanced Photoshop filters could be implemented in hardware potentially any Photoshop filter