15 213 Memory Technology March 14 2000 Topics class17 ppt Memory Hierarchy Basics Static RAM Dynamic RAM Magnetic Disks Access Time Gap Computer System Processor Processor Reg Cache Cache Memory I O Memory I Obus bus Memory Memory I O I O controller controller Disk class17 ppt Disk 2 I O I O controller controller I O I O controller controller Display Display Network Network CS 213 S 00 Levels in Memory Hierarchy cache CPU CPU regs regs Register size speed Mbyte block size 200 B 2 ns 8B 8B C a c h e 32 B Cache virtual memory Memory Memory Memory 32KB 4MB 4 ns 100 MB 32 B 128 MB 60 ns 1 50 MB 8 KB 8 KB disk disk Disk Memory 20 GB 8 ms 0 05 MB larger slower cheaper class17 ppt 3 CS 213 S 00 Scaling to 0 1 m Semiconductor Industry Association 1992 Technology Workshop Projected future technology based on past trends 1992 Feature size 1995 0 5 1998 0 35 2001 0 25 2004 0 18 0 12 2007 0 10 Industry is slightly ahead of projection DRAM capacity 16M 16G 64M 256M 1G 4G Doubles every 1 5 years Prediction on track Chip area cm2 12 5 2 5 4 0 6 0 8 0 10 0 Way off Chips staying small class17 ppt 4 CS 213 S 00 Static RAM SRAM Fast 4 nsec access time Persistent as long as power is supplied no refresh required Expensive 100 MByte 6 transistors bit Stable High immunity to noise and environmental disturbances Technology for caches class17 ppt 5 CS 213 S 00 Anatomy of an SRAM Cell bit line b bit line b word line Stable Configurations 0 1 Terminology bit line carries data word line used for addressing 6 transistors Write Read 1 set bit lines to new data value b is set to the opposite of b 2 raise word line to high sets cell to new state may involve flipping relative to old state class17 ppt 1 6 1 set bit lines high 2 set word line high 3 see which bit line goes low CS 213 S 00 0 SRAM Cell Principle Inverter Amplifies Negative gain Slope 1 in middle Saturates at ends Inverter Pair Amplifies Positive gain Slope 1 in middle Saturates at ends 1 0 9 0 8 0 7 0 6 0 5 V1 V2 0 4 0 3 0 2 Vin 0 1 V1 0 0 V2 class17 ppt 0 2 0 4 0 6 0 8 1 Vin 7 CS 213 S 00 Bistable Element Stability Vin V1 V2 1 Stable 0 9 Require Vin V2 Stable at endpoints recover from pertubation Metastable in middle Fall out when perturbed Ball on Ramp Analogy 0 8 0 7 0 6 Metastable 0 5 Vin 0 4 V2 0 3 0 2 0 1 0 0 0 2 Stable class17 ppt 0 4 0 6 0 8 1 Vin 0 8 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 CS 213 S 00 0 9 1 Example SRAM Configuration 16 x 8 W0 A0 A1 A2 b7 b7 b1 b1 b0 b0 W1 Address Address decoder decoder A3 memory cells W15 sense write sense write amps amps Input output lines d7 class17 ppt sense write sense write amps amps d1 9 sense write sense write amps amps d0 CS 213 S 00 R W Dynamic RAM DRAM Slower than SRAM access time 60 nsec Nonpersistant every row must be accessed every 1 ms refreshed Cheaper than SRAM 1 50 MByte 1 transistor bit Fragile electrical noise light radiation Workhorse memory technology class17 ppt 10 CS 213 S 00 Anatomy of a DRAM Cell Word Line Bit Line Access Transistor Storage Node Cnode CBL Writing Reading Word Line Bit Line Word Line Bit Line V V Cnode CBL Storage Node class17 ppt 11 CS 213 S 00 Addressing Arrays with Bits Array Size R rows R 2r C columns C 2c N R C bits of memory Addressing address Addresses are n bits where N 2n row address address C leftmost r bits of address col address address C rightmost bits of address r c row col n Example R 2 C 4 address 6 0 1 0 000 100 1 001 101 row 1 class17 ppt 12 2 010 110 3 011 111 col 2 CS 213 S 00 Example 2 Level Decode DRAM 64Kx1 RAS 256 Rows row Row Row address address latch latch 8 Row Row decoder decoder 256 Columns A7 A0 column column R W sense write sense write amps amps col Provide 16bit address in two 8 bit chunks Column Column address address latch latch column column latch latchand and decoder decoder 8 CAS class17 ppt 256x256 256x256 cell cellarray array 13 DoutDin CS 213 S 00 DRAM Operation Row Address 50ns Set Row address on address lines strobe RAS Entire row read stored in column latches Contents of row of memory cells destroyed Column Address 10ns Set Column address on address lines strobe CAS Access selected bit READ transfer from selected column latch to Dout WRITE Set selected column latch to Din Rewrite 30ns Write back entire row class17 ppt 14 CS 213 S 00 Timing Observations About DRAMs Access time 60ns cycle time 90ns Need to rewrite row Must Refresh Periodically Perform complete memory cycle for each row Approximately once every 1ms Sqrt n cycles Handled in background by memory controller Inefficient Way to Get a Single Bit Effectively read entire row of Sqrt n bits class17 ppt 15 CS 213 S 00 Enhanced Performance Conventional Access DRAMs RAS Row Col RAS CAS RAS CAS Page Mode Row Row address address latch latch 8 Row Row decoder decoder 256x256 256x256 cell array cell array row Row Series of columns A7 A0 RAS CAS CAS CAS col Gives successive bits Other Acronyms sense write sense write amps amps Column Column address address latch latch 8 R W column column latch and latch and decoder decoder EDORAM CAS Extended data output SDRAM Entire row buffered here Synchronous DRAM Typical Performance row access time cycle time 50ns class17 ppt col access time cycle time 10ns 90ns 16 page mode 25ns CS 213 S 00 Video RAM Performance Enhanced for Video Graphics Operations Frame buffer to hold graphics image Writing Random access of bits 256x256 256x256 Also supports rectangle fill operations cell cellarray array Set all bits in region to 0 or 1 Reading Load entire row into shift register column column sense write Shift out at video rates sense write Performance Example 1200 X 1800 pixels frame 24 bits pixel 60 frames second 2 8 GBits second class17 ppt 17 amps amps Shift ShiftRegister Register Video Stream Output CS 213 S 00 Capacity DRAM Driving Forces 4X per generation Square array of cells Typical scaling Lithography dimensions 0 7X Areal density 2X Cell function packing 1 5X Chip area 1 33X Scaling challenge Typically Cnode CBL 0 1 0 2 Must keep Cnode high as shrink cell size Retention Time Typically 16 256 ms Want higher for low power applications class17 ppt …
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