Random Access Memory RAM 15 213 Key features The course that gives CMU its Zip RAM is packaged as a chip Basic storage unit is a cell one bit per cell The Memory Hierarchy Oct 4 2001 Multiple RAM chips form a memory Static RAM SRAM Each cell stores bit with a six transistor circuit Retains value indefinitely as long as it is kept powered Relatively insensitive to disturbances such as electrical noise Topics Faster and more expensive than DRAM Storage technologies and trends Locality of reference Caching in the memory hierarchy Dynamic RAM DRAM Each cell stores bit with a capacitor and transistor Value must be refreshed every 10 100 ms Sensitive to disturbances Slower and cheaper than SRAM class12 ppt class12 ppt SRAM vs DRAM summary 2 CS 213 F 01 Conventional DRAM organization d x w DRAM dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip SRAM DRAM Tran per bit Access time Persist Sensitive Cost Applications 6 1 1X 10X 100x 1X cache memories Main memories frame buffers Yes No No Yes cols 0 2 bits 1 2 3 0 addr 1 rows memory controller 2 supercell 2 1 to CPU 8 bits 3 data internal row buffer class12 ppt 3 CS 213 F 01 class12 ppt 4 CS 213 F 01 Reading DRAM supercell 2 1 Reading DRAM supercell 2 1 Step 1 a Row access strobe RAS selects row 2 Step 1 b Row 2 copied from DRAM array to row buffer Step 2 a Column access strobe CAS selects column 1 Step 2 b Supercell 2 1 copied from buffer to data lines and eventually back to the CPU 16 x 8 DRAM chip 16 x 8 DRAM chip cols cols 0 RAS 2 2 1 2 3 0 CAS 1 2 0 addr 2 3 0 addr 1 1 rows memory controller 1 memory controller 2 rows supercell 2 1 3 8 8 data 2 3 data row 2 internal row buffer class12 ppt 5 CS 213 F 01 internal row buffer class12 ppt Memory modules 6 CS 213 F 01 Enhanced DRAMs addr row i col j supercell i j All enhanced DRAMs are built around the conventional DRAM core Fast page mode DRAM FPM DRAM DRAM 0 64 MB memory module consisting of eight 8Mx8 DRAMs DRAM 7 data intern Access contents of row with RAS CAS CAS CAS CAS instead of RAS CAS RAS CAS RAS CAS RAS CAS Extended data out DRAM EDO DRAM Enhanced FPM DRAM with more closely spaced CAS signals Synchronous DRAM SDRAM Driven with rising clock edge instead of asynchronous control signals bits bits bits bits bits bits bits 56 63 48 55 40 47 32 39 24 31 16 23 8 15 bits 0 7 Double data rate synchronous DRAM DDR SDRAM Enhancement of SDRAM that uses both clock edges as control signals 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 64 bit doubleword at main memory address A Memory controller Video RAM VRAM Like FPM DRAM but output is produced by shifting row buffer Dual ported allows concurrent reads and writes 64 bit doubleword to CPU chip class12 ppt 7 CS 213 F 01 class12 ppt 8 CS 213 F 01 Nonvolatile memories Bus structure connecting CPU and memory DRAM and SRAM are volatile memories Lose information if powered off Nonvolatile memories retain value even if powered off Generic name is read only memory ROM Misleading because some ROMs can be read and modified Types of ROMs A bus is a collection of parallel wires that carry address data and control signals Buses are typically shared by multiple devices CPU chip Programmable ROM PROM register file Eraseable programmable ROM EPROM Electrically eraseable PROM EEPROM ALU Flash memory memory bus system bus Firmware Program stored in a ROM Boot time code BIOS basic input ouput system graphics cards disk controllers class12 ppt 9 class12 ppt CS 213 F 01 Memory read transaction 1 eax ALU bus interface class12 ppt register file eax A main memory 0 x 11 CS 213 F 01 Main memory reads A from the memory bus retreives word x and places it on the bus Load operation movl A eax I O bridge 10 Memory read transaction 2 CPU places address A on the memory bus register file main memory I O bridge bus interface CS 213 F 01 A Load operation movl A eax ALU I O bridge bus interface class12 ppt x main memory 0 x 12 A CS 213 F 01 Memory read transaction 3 Memory write transaction 1 CPU read word x from the bus and copies it into register eax register file eax CPU places address A on bus Main memory reads it and waits for the corresponding data word to arrive register file Load operation movl A eax ALU x eax bus interface x 13 I O bridge y register file ALU eax y y main memory 0 A 15 CS 213 F 01 Main memory read data word y from the bus and stores it at address A bus interface class12 ppt 14 Memory write transaction 3 Store operation movl eax A I O bridge main memory 0 A class12 ppt CS 213 F 01 CPU places data word y on the bus eax A bus interface A Memory write transaction 2 register file ALU y main memory 0 I O bridge class12 ppt Store operation movl eax A CS 213 F 01 Store operation movl eax A ALU I O bridge bus interface class12 ppt main memory 0 y 16 CS 213 F 01 A Disk geometry Disk geometry muliple platter view Disks consist of platters each with two surfaces Each surface consists of concentric rings called tracks Each track consists of sectors separated by gaps Aligned tracks form a cylinder cylinder k surface 0 tracks surface track k gaps platter 0 surface 1 surface 2 platter 1 surface 3 surface 4 platter 2 surface 5 spindle spindle sectors class12 ppt 17 CS 213 F 01 Disk capacity class12 ppt Vendors express capacity in units of gigabytes GB where 1 GB 10 6 Capacity is determined by these technology factors Recording density bits in number of bits that can be squeezed into a 1 inch segment of a track Capacity bytes sector x avg sectors track x tracks surface x surfaces platter x platters disk Example 512 bytes sector 300 sectors track on average Track density tracks in number of tracks that can be squeezed into a 1 inch radial segment 20 000 tracks surface Areal density bits in2 product of recording and track density 2 surfaces platter Modern disks partition tracks into disjoint subsets called recording zones Each track in a zone has the same number of sectors determined by the circumference of innermost track Each zone has a different number of sectors track 19 CS 213 F 01 Computing disk capacity Capacity maximum number of bits that can be stored class12 ppt 18 CS 213 F 01 5 platters disk Capacity 512 x 300 x 20000 x 2 x 5 30 720 000 000 …
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