15 213 Pentium III Linux Memory System April 4 2000 Topics class21 ppt P III address translation Linux memory management Linux page fault handling memory mapping Pentium III Memory System DRAM external system bus e g PCI L2 cache cache bus inst TLB bus interface unit instruction fetch unit data TLB L1 i cache L1 d cache processor package class21 ppt 2 32 bit address space 4 KB pagesize L1 L2 and TLBs 4 way set associative inst TLB 32 entries 8 sets data TLB 64 entries 16 sets L1 i cache and d cache 16 KB 32 B linesize 128 sets L2 cache unified 128 KB 2 MB CS 213 S 00 Review of Abbreviations Symbols Components of the virtual address VA TLBI TLB index TLBT TLB tag VPO virtual page offset VPN virtual page number Components of the physical address PA PPO physical page offset same as VPO PPN physical page number CO byte offset within cache line CI cache index CT cache tag class21 ppt 3 CS 213 S 00 Overview of P III Address Translation 32 result CPU 20 VPN 12 virtual address VA VPO L1 128 sets 4 lines set TLB hit TLB 16 sets 4 entries set 10 10 VPN1 VPN2 20 PPN PDE PDBR L1 miss L1 hit 16 4 TLBT TLBI TLB miss L2 andDRAM 20 CT 12 PPO 7 5 CI CO physical address PA PTE Page tables class21 ppt 4 CS 213 S 00 Pentium III 2 level Page Table Structure Page directory 1024 page tables 1024 4 byte page directory entries PDEs that point to page tables one page directory per process page directory must be in memory when its process is running always pointed to by PDBR 1024 PTEs Page tables 1024 PDEs 1024 PTEs 1024 4 byte page table entries PTEs that point to pages page tables can be paged in and out class21 ppt page directory 1024 PTEs 5 CS 213 S 00 Pentium III Page Directory Entry PDE 31 12 11 Page table physical base addr 9 Avail 8 7 G PS 6 5 A 4 3 2 1 0 CD WT U S R W P 1 Page table physical base address 20 most significant bits of physical page table address forces page tables to be 4KB aligned Avail available for system programmers G global page don t evict from TLB on task switch PS page size 4K 0 or 4M 1 A accessed set by MMU on reads and writes cleared by software CD cache disabled 1 or enabled 0 WT write through or write back cache policy for this page table U S user or supervisor mode access R W read only or read write access P page table is present in memory 1 or not 0 31 1 Available for OS page table location in secondary storage class21 ppt 6 0 P 0 CS 213 S 00 Pentium III Page Table Entry PTE 31 12 11 Page physical base address 9 Avail 8 7 6 5 G 0 D A 4 3 2 1 0 CD WT U S R W P 1 Page base address 20 most significant bits of physical page address forces pages to be 4 KB aligned Avail available for system programmers G global page don t evict from TLB on task switch D dirty set by MMU on writes A accessed set by MMU on reads and writes CD cache disabled or enabled WT write through or write back cache policy for this page U S user supervisor R W read write P page is present in physical memory 1 or not 0 31 1 Available for OS page location in secondary storage class21 ppt 7 0 P 0 CS 213 S 00 How Pentium III Page Tables Map Virtual Addresses to Physical Ones 10 VPN1 10 VPN2 word offset into page directory 12 VPO word offset into page table page directory PDE physical address of page table base if P 1 20 physical address of page base if P 1 12 PPO PPN class21 ppt word offset into physical and virtual page page table PTE PDBR physical address of page directory Virtual address 8 Physical address CS 213 S 00 Pentium III TLB translation 32 result CPU 20 VPN 12 virtual address VA VPO L1 128 sets 4 lines set TLB hit TLB 16 sets 4 entries set 10 10 VPN1 VPN2 20 PPN PDE PDBR L1 miss L1 hit 16 4 TLBT TLBI TLB miss L2 andDRAM 20 CT 12 PPO 7 5 CI CO physical address PA PTE Page tables class21 ppt 9 CS 213 S 00 Pentium III TLB TLB entry not all documented so this is speculative 32 16 1 1 PDE PTE Tag PD V V indicates a valid 1 or invalid 0 TLB entry PD is this entry a PDE 1 or a PTE 0 tag disambiguates entries cached in the same set PDE PTE page directory or page table entry Structure of the data TLB 16 sets 4 entries set class21 ppt entry entry entry entry entry entry entry entry entry entry entry entry entry entry set 0 set 1 set 2 entry entry set 15 10 CS 213 S 00 Translating with the Pentium III TLB CPU 20 VPN 12 virtual address VPO 16 4 TLBT TLBI 1 TLB miss 2 PDE page table translation TLB PTE hit 3 20 PPN physical address 4 class21 ppt 12 PPO 11 1 Partition VPN into TLBT and TLBI 2 Is the PTE for VPN cached in set TLBI 3 Yes then build physical address 4 No then read PTE and PDE if not cached from memory and build physical address CS 213 S 00 Pentium III Page Table Translation 32 result CPU 20 VPN 12 virtual address VA VPO L1 128 sets 4 lines set TLB hit TLB 16 sets 4 entries set 10 10 VPN1 VPN2 20 PPN PDE PDBR L1 miss L1 hit 16 4 TLBT TLBI TLB miss L2 andDRAM 20 CT 12 PPO 7 5 CI CO physical address PA PTE Page tables class21 ppt 12 CS 213 S 00 Translating with the P III Page Tables Case 1 1 20 VPN 12 VPO 20 PPN VPN1 VPN2 12 PPO Mem PDE p 1 PTE p 1 data Case 1 1 page table and page present MMU Action MMU build physical address and fetch data word OS action PDBR Page directory Page table Data page none Disk class21 ppt 13 CS 213 S 00 Translating with the P III Page Tables Case 1 0 20 VPN Case 1 0 page table present but page missing MMU Action 12 VPO VPN1 VPN2 PDE p 1 PTE p 0 Page directory Page table Mem PDBR data Disk page fault exception handler receives the following args VA that caused fault fault caused by nonpresent page or page level protection violation read write user supervisor Data page class21 ppt 14 CS 213 S 00 Translating with the P III Page Tables Case 1 0 Cont 20 VPN OS Action 12 VPO 20 PPN VPN1 VPN2 Mem 12 PPO PDE p 1 PTE p 1 data Page directory Page table …
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