Carnegie Mellon Machine Level Programming I Basics 15 213 18 243 Introduc3on to Computer Systems 4th Lecture Sep 2 2010 Instructors Randy Bryant and Dave O Hallaron 1 Carnegie Mellon Today Machine Programming I Basics History of Intel processors and architectures C assembly machine code Assembly Basics Registers operands move Intro to x86 64 2 Carnegie Mellon Intel x86 Processors Totally dominate laptop desktop server market EvoluJonary design Backwards compa3ble up un3l 8086 introduced in 1978 Added more features as 3me goes on Complex instrucJon set computer CISC Many di erent instruc3ons with many di erent formats But only small subset encountered with Linux programs Hard to match performance of Reduced Instruc3on Set Computers RISC But Intel has done just that In terms of speed Less so for low power 3 Carnegie Mellon Intel x86 EvoluJon Milestones Name 8086 Date 1978 Transistors 29K MHz 5 10 First 16 bit processor Basis for IBM PC DOS 1MB address space 386 1985 275K 16 33 First 32 bit processor referred to as IA32 Added at addressing Capable of running Unix 32 bit Linux gcc uses no instruc3ons introduced in later models PenJum 4F 2004 125M 2800 3800 First 64 bit processor referred to as x86 64 Core i7 2008 731M 2667 3333 Our shark machines 4 Carnegie Mellon Intel x86 Processors Overview Architectures X86 16 Processors 8086 286 X86 32 IA32 MMX 386 486 PenJum PenJum MMX SSE PenJum III SSE2 PenJum 4 SSE3 PenJum 4E X86 64 EM64t PenJum 4F SSE4 Core 2 Duo Core i7 Jme IA o en rede ned as latest Intel architecture 5 Carnegie Mellon Intel x86 Processors contd Machine EvoluJon 386 Pen3um Pen3um MMX Pen3umPro Pen3um III Pen3um 4 Core 2 Duo Core i7 1985 1993 1997 1995 1999 2001 2006 2008 0 3M 3 1M 4 5M 6 5M 8 2M 42M 291M 731M Added Features Instruc3ons to support mul3media opera3ons Parallel opera3ons on 1 2 and 4 byte data both integer FP Instruc3ons to enable more e cient condi3onal opera3ons Linux GCC EvoluJon Two major steps 1 support 32 bit 386 2 support 64 bit x86 64 6 Carnegie Mellon More InformaJon Intel processors Wikipedia Intel microarchitectures 7 Carnegie Mellon New Species ia64 then IPF then Itanium Name Itanium Date 2001 Transistors 10M First shot at 64 bit architecture rst called IA64 Radically new instruc3on set designed for high performance Can run exis3ng IA32 programs On board x86 engine Joint project with Hewlef Packard Itanium 2 2002 221M Big performance boost Itanium 2 Dual Core 2006 1 7B Itanium has not taken o in marketplace Lack of backward compa3bility no good compiler support Pen3um 4 got too good 8 Carnegie Mellon x86 Clones Advanced Micro Devices AMD Historically AMD has followed just behind Intel A lifle bit slower a lot cheaper Then Recruited top circuit designers from Digital Equipment Corp and other downward trending companies Built Opteron tough compe3tor to Pen3um 4 Developed x86 64 their own extension to 64 bits 9 Carnegie Mellon Intel s 64 Bit Intel Adempted Radical Shi from IA32 to IA64 Totally di erent architecture Itanium Executes IA32 code only as legacy Performance disappoin3ng AMD Stepped in with EvoluJonary SoluJon x86 64 now called AMD64 Intel Felt Obligated to Focus on IA64 Hard to admit mistake or that AMD is befer 2004 Intel Announces EM64T extension to IA32 Extended Memory 64 bit Technology Almost iden3cal to x86 64 All but low end x86 processors support x86 64 But lots of code s3ll runs in 32 bit mode 10 Carnegie Mellon Our Coverage IA32 The tradi3onal x86 x86 64 EM64T The emerging standard PresentaJon Book presents IA32 in Sec3ons 3 1 3 12 Covers x86 64 in 3 13 We will cover both simultaneously Some labs will be based on x86 64 others on IA32 11 Carnegie Mellon Today Machine Programming I Basics History of Intel processors and architectures C assembly machine code Assembly Basics Registers operands move Intro to x86 64 12 Carnegie Mellon De niJons Architecture also instrucJon set architecture ISA The parts of a processor design that one needs to understand to write assembly code Examples instruc3on set speci ca3on registers Microarchitecture ImplementaJon of the architecture Examples cache sizes and core frequency Example ISAs Intel x86 IA IPF 13 Carnegie Mellon Assembly Programmer s View CPU PC Registers CondiJon Codes Addresses Data Instruc3ons Address of next instruc3on Called EIP IA32 or RIP x86 64 Register le Heavily used program data Condi3on codes Object Code Program Data OS Data Stack Programmer Visible State PC Program counter Memory Store status informa3on about most recent arithme3c opera3on Used for condi3onal branching Memory Byte addressable array Code user data some OS data Includes stack used to support procedures 14 Carnegie Mellon Turning C into Object Code Code in les p1 c p2 c Compile with command gcc O1 p1 c p2 c o p Use basic op3miza3ons O1 Put resul3ng binary in le p text C program p1 c p2 c Compiler gcc S text Asm program p1 s p2 s Assembler gcc or as binary Object program p1 o p2 o Linker gcc or ld binary StaJc libraries a Executable program p 15 Carnegie Mellon Compiling Into Assembly C Code int sum int x int y int t x y return t Generated IA32 Assembly sum pushl ebp movl esp ebp movl 12 ebp eax addl 8 ebp eax popl ebp ret Some compilers use instrucJon leave Obtain with command usr local bin gcc O1 S code c Produces le code s 16 Carnegie Mellon Assembly CharacterisJcs Data Types Integer data of 1 2 or 4 bytes Data values Addresses untyped pointers FloaJng point data of 4 8 or 10 bytes No aggregate types such as arrays or structures Just con3guously allocated bytes in memory 17 Carnegie Mellon Assembly CharacterisJcs OperaJons Perform arithmeJc funcJon on register or memory data Transfer data between memory and register Load data from memory into register Store register data into memory Transfer control Uncondi3onal jumps to from procedures Condi3onal branches 18 Carnegie Mellon Object Code Code for sum 0x401040 sum 0x55 0x89 0xe5 0x8b 0x45 0x0c 0x03 0x45 0x08 Total of 11 bytes 0x5d 0xc3 Each instrucJon 1 2 or 3 bytes Starts at address 0x401040 Assembler Translates s into o Binary encoding of each instruc3on Nearly complete image of executable code Missing linkages between code in di erent les Linker Resolves references between les Combines with sta3c run 3me libraries E g code for malloc printf Some libraries are dynamically linked Linking occurs when program begins execu3on 19 Carnegie Mellon Machine InstrucJon Example int t x y Add two signed integers Long words in GCC parlance Same instruc3on whether signed
View Full Document
Unlocking...