University of Toronto ECE532 Digital Hardware Module 10 Fast Simplex Link FSL Interfaces Version 1 1 For EDK 6 2i 12 1 2004 Goals To learn about the Xilinx Fast Simplex Link FSL Interface To become familiar with the documentation you will need to refer to when designing your own systems with FSLs Introduction This module will differ from the more step by step modules as there is a Xilinx application that covers how to connect user IP to the Microblaze FSL bus system This module is more of a guide through that example Background The FSL is a uni directional point to point connection between 2 devices that Xilinx considers to be a bus It is essentially an abstracted glorified FIFO with a standardized interface The implementation differs depending on if the user needs it to be synchronous Both devices run on the same clock or asynchronous the master and slave run on different clocks on the size and on some other parameters that the user can specify A single FSL can connect only 1 master device to 1 slave device The master writes into the FSL and the slave reads from it Since we typically want to be able to communicate in both directions FSLs are often used in pairs where each of the 2 connected devices is a master on one of the FSLs and a slave on the other Requirements Access to ISE 6 2 03i EDK 6 2 2i and the Xilinx Multimedia development board Modules 1 6 so that you have a good working knowledge of EDK pcores and ISE Preparation Read the FSL datasheet EDK installation dir hw XilinxProcessorIPLib pcores fsl v20 v2 00 a doc fsl v20 pdf 1 University of Toronto ECE532 Digital Hardware Module 10 Fast Simplex Link FSL Interfaces Read the FSL Application Note XAPP529 http www xilinx com bvdocs appnotes xapp529 pdf If you are short on time start reading at the middle of page 6 where they begin to describe the FSL interface in detail Guiding You Through XAPP529 Download the reference design for XAPP529 at www xilinx com bvdocs appnotes xapp529 6 2 zip Open the project and open the Add Edit Cores dialog Notice that in the Peripherals tab EDK has included the XAPP529 core xil idct but not the FSLs The FSLs are considered to be buses in EDK Go to the Bus Connections tab This is where you add instances of the FSL and connect the devices to the FSLs Do not use fsl v20 v1 00 b it only includes the synchronous SRL FIFO version of the FSL which can only be exactly 32 bits wide and 16 words deep The fsl v20 v2 00 a version includes the SRL FIFO version but also can be used in with other depths other physical resources and asynchronously if needed In this tab you can see the FSL bus interfaces for the XAPP529 core and 2 pairs of FSL bus interfaces for Microblaze You connect them to the FSLs here Go to the Parameters tab Select the MicroBlaze instance in the dropdown box The parameter C FSL LINKS dictates how many pairs of FSL connections are available in the Bus Connections tab In this design it is set to 2 even though only 1 FSL link is needed If you select one of the FSL instances you can set its parameters The XAPP529 design uses the older version of the FSL so less parameters are available to customize Important Notes Note that you can only have 1 master and 1 slave on a single FSL Note that 1 FSL link is composed of 1 pair of FSLs If the FSL link connects devices A and B one of the FSLs has device A as the master and B as the slave The other FSL has B as the master and A as the slave Do not write to the FSL when the Full signal is high Doing so will cause the FSL data to be corrupted In the asynchronous FSL doing so will overwrite the word in FSL S Data with the latest data word This is not a concern when doing writes in C code because the MicroBlaze functions take care of checking the FSL Full and Exists lines 2
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