Announcements 15 213 Recitation room changes The course that gives CMU its Zip The Memory Hierarchy Feb 14 2008 C Nate Doherty 1211 G Pratyusa Porter A22 H Ally Porter A19 Exam date change Topics Storage technologies and trends Locality of reference Caching in the memory hierarchy NOT Thursday 2 21 CHANGED TO Tuesday 2 26 7 00 p m 8 30 p m UC McConomy XOR Wean 7500 expect e mail Calculator policy Calculators will not be needed on the exam hence forbidden Collaboration reminder Writing code together counts as sharing code forbidden Talking through a problem can include pictures not code 2 class10 ppt 15 213 S 08 Opinion Poll Outline Plan A RAM 2 14 2 19 2 21 2 26 2 28 Thu Linking DAE Thu Memory Hierarchy DAE Tue Opt II REB Thu No class Bill Gates Tue Cache Memories DAE Evening Exam ROM Disks Mind the gap Back to original schedule Locality Memory Hierarchy Plan B Caches 2 14 Thu Memory Hierarchy DAE 2 19 Tue Opt II REB 2 21 Thu Cache Memories DAE Bill Gates 2 26 Tue No class 2 28 Thu Linking DAE Evening Exam Back to original schedule 3 15 213 S 08 Random Access Memory RAM 4 15 213 S 08 SRAM vs DRAM Summary Key features RAM is traditionally packaged as a chip Basic storage unit is normally a cell one bit per cell Multiple RAM chips form a memory Tran per bit Access Needs Needs time refresh EDC SRAM 4 or 6 1X No Maybe 100x cache memories DRAM 1 10X Yes Yes Main memories frame buffers Static RAM SRAM SRAM Each cell stores a bit with a four or six transistor circuit Retains value indefinitely as long as it is kept powered Relatively insensitive to electrical noise EMI radiation etc Faster and more expensive than DRAM Cost 1X Applications Dynamic RAM DRAM DRAM 5 Each cell stores bit with a capacitor One transistor is used for access Value must be refreshed every 10 100 ms More sensitive to disturbances EMI radiation than SRAM Slower and cheaper than SRAM 15 213 S 08 6 15 213 S 08 Conventional DRAM Organization Step 1 a Row access strobe RAS RAS selects row 2 d x w DRAM Reading DRAM Supercell 2 1 dw total bits organized as d supercells of size w bits Step 1 b Row 2 copied from DRAM array to row buffer 16 x 8 DRAM chip 16 x 8 DRAM chip cols cols 0 2 bits 1 2 3 0 RAS 2 2 0 1 2 3 0 addr addr 1 1 rows memory controller 2 supercell 2 1 to CPU rows memory controller 2 3 8 bits 3 8 data data internal row buffer 7 15 213 S 08 Reading DRAM Supercell 2 1 internal row buffer 8 Memory Modules Step 2 a Column access strobe CAS CAS selects column 1 addr row i col j supercell i j Step 2 b Supercell 2 1 copied from buffer to data lines and eventually back to the CPU DRAM 0 64 MB memory module consisting of eight 8Mx8 DRAMs 16 x 8 DRAM chip cols 0 CAS 1 2 1 DRAM 7 2 15 213 S 08 3 0 addr To CPU 1 bits bits bits bits bits bits bits 56 63 48 55 40 47 32 39 24 31 16 23 8 15 rows memory controller bits 0 7 2 63 supercell 2 1 8 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 3 64 bit doubleword at main memory address A Memory controller data 64 bit doubleword supercell 2 1 9 internal row buffer 15 213 S 08 10 15 213 S 08 Enhanced DRAMs Nonvolatile Memories DRAM Cores with better interface logic and faster I O DRAM and SRAM are volatile memories Synchronous DRAM SDRAM Double data rate synchronous DRAM DDR SDRAM Uses a conventional clock signal instead of asynchronous control Double edge clocking sends two bits per cycle per pin RamBus DRAM RDRAM Uses faster signaling over fewer wires source directed clocking with a Transaction oriented interface protocol Obsolete Technologies Fast page mode DRAM FPM DRAM Allowed re use of row addresses Extended data out DRAM EDO DRAM Video RAM VRAM Dual ported FPM DRAM with a second concurrent serial interface Extra functionality DRAMS CDRAM GDRAM Added SRAM CDRAM and support for graphics operations GDRAM 11 Read only memory ROM programmed during production Magnetic RAM MRAM stores bit magnetically in development Ferro electric RAM FERAM uses a ferro electric dielectric Programmable ROM PROM can be programmed once Eraseable PROM EPROM can be bulk erased UV X Ray Electrically eraseable PROM EEPROM electronic erase capability Flash memory EEPROMs with partial sector erase capability Uses for Nonvolatile Memories Enhanced FPM DRAM with more closely spaced CAS signals Lose information if powered off Nonvolatile memories retain value even if powered off 15 213 S 08 12 Firmware programs stored in a ROM BIOS controllers for disks network cards graphics accelerators security subsystems Solid state disks flash cards memory sticks etc Smart cards embedded systems appliances Disk caches 15 213 S 08 Traditional Bus Structure Connecting CPU and Memory A bus is a collection of parallel wires that carry address data and control signals Memory Read Transaction 1 CPU places address A on the memory bus Buses are typically shared by multiple devices register file Load operation movl A eax ALU eax CPU chip register file I O bridge system bus main memory 0 main memory 13 15 213 S 08 14 15 213 S 08 Memory Read Transaction 2 Memory Read Transaction 3 Main memory reads A from the memory bus retrieves word x and places it on the bus CPU read word x from the bus and copies it into register eax register file register file Load operation movl A eax ALU eax eax I O bridge x bus interface x Load operation movl A eax ALU main memory 0 x 15 main memory 0 I O bridge bus interface A 15 213 S 08 16 15 213 S 08 Memory Write Transaction 2 CPU places address A on bus Main memory reads it and waits for the corresponding data word to arrive CPU places data word y on the bus register file y eax I O bridge bus interface 17 register file Store operation movl eax A ALU A y main memory 0 15 213 S 08 Store operation movl eax A ALU I O bridge bus interface A 18 A x Memory Write Transaction 1 eax A x memory bus I O bridge bus interface A bus interface ALU y main memory 0 A 15 213 S 08 Memory Write Transaction 3 Memory Subsystem Trends Main memory reads data word y from the bus and stores it at address A Observation A DRAM chip has an access time of about 50ns Traditional systems may need 3x longer to get the data from memory into a CPU register register file eax y Store operation movl eax A ALU I O bridge main memory 0 Modern systems integrate the memory controller onto the CPU …
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