University of Toronto ECE532 Digital Hardware Using External ZBT Memory Version 0 02a For EDK 6 2 2 November 30 2004 Goals You will be learning how to connect a design to external memory Background In previous designs you have used internal memory structures instantiated within the FPGA This memory has been connected to the LMB the Local Memory Bus The external memory on the Multimedia Board is ZBT memory and will be connected to the system with the OPB On chip Peripheral Bus External memory can be connected to an EDK system using Xilinx s External Memory Controller EMC core The EMC is an OPB peripheral that can connect up to 8 external banks into the address space of the MicroBlaze The Base System Builder wizzard has the ability to create a design that contains a connection to a single ZBT bank The design provided by the Base System Builder works However it does not properly synchronize the memory clock In more complicated designs the clock synchronization becomes very relevant This document describes the method used to upgrade the design provided by the Base System Builder so that the clock to the external memory is properly synchronized Since the memory is external to the FPGA the delays associated with signals are large and cannot be predicted by the FPGA tools This problem is overcome using a feedback wire built into to the Multimedia Board s PCB that is the correct length to provide the correct delay Input from this feedback wire can be used to adjust the clock driving the external memory The Multimedia board contains a total of 5 banks of ZBT memory providing 10Mb of space After learning how to use the EMC to connect to a single bank this document will address how to connect all 5 Requirements Module 1 Building a Base System Module 2 Adding Drivers and IP Preparation Summaries of how to connect external memories are given in the Connecting to Memory section of the documentation for the OPB External Memory Controller Core You might also want to look at the Xilinx DCM Digital Clock Manager documentation found in the Virtex II FPGA data sheet Connecting a Single ZBT Bank Step by step 1 Create a new system with Base System Builder as you normally would Ensure that in ZBT 512Kx32 is selected with the OPB EMC option in the Configure Additional IO Interfaces screen You may also wish to select Generate Sample Application and Linker Script in the Software Configuration screen as the application includes a test of the ZBT memory 2 Open the Add Edit Cores dialog and add two instances of dcm module The two DCM modules will be used to create the clocking scheme shown in Figure 1 Add the following to the ports table for each of the DCM modules CLKIN CLKFB RST DSSEN PSEN CLK0 LOCKED Set them all as internal in scope 1 University of Toronto ECE532 Digital Hardware Using External ZBT Memory External Clock OPB Clk CLK0 CLKIN CLK0 CLKIN OBUF CLKFB Syncmem Clk fb CLKFB BUFG DCM FPGA DCM Syncmem Clk Synchronous Memory Bank CLK Figure 1 The clocking scheme required for external ZBT memory with clock feedback Taken from Xilinx s OPB EMC datasheet Connect the ports of the first DCM module to the following nets dcm rst sys clk predcm sys clk s net gnd net gnd sys clk s opb dcm locked RST CLKIN CLKFB PSEN DSSEN CLK0 LOCKED Connect the ports of the second DCM modules to the following nets RST CLKIN CLKFB PSEN DSSEN CLK0 LOCKED dcm rst sys clk s zbt dcm feedback net gnd net gnd zbt dcm clk zbt dcm locked 3 Locate the system port that connects the external sys clk pin to the net sys clk s Change the net to sys clk predcm 4 Using the Add Port button create an output port named ZBT 512Kx32 EMC CLK FEEDBACK OUT and an input port named ZBT 512Kx32 EMC CLK FEEDBACK IN It is not necessary to classify the ports as CLK signals Connect the two new ports to the zbt dcm clk and zbt dcm feedback nets respectively Change the C CLKIN PERIOD parameter for each DCM to 37 037 The default values for the other parameters should be sufficient The DCM will lock when the edges of its CLKFB and CLKIN inputs are aligned 5 Locate the generated port ZBT 512Kx32 EMC CLK OUT This was generated by System Builder Notice that it is by default connected to sys clk s Connect it to zbt dcm clk instead 6 Edit the system ucf file to connect the two new ports to appropriate pins This can be accomplished by adding the following lines 2 University of Toronto ECE532 Digital Hardware Using External ZBT Memory Net Net Net Net ZBT 512Kx32 EMC CLK FEEDBACK IN LOC AE15 ZBT 512Kx32 EMC CLK FEEDBACK IN FAST ZBT 512Kx32 EMC CLK FEEDBACK OUT LOC AH14 ZBT 512Kx32 EMC CLK FEEDBACK OUT FAST 7 The DCM takes time to synchronize the clocks and lock During this time it is undesirable for the MicroBlaze or other components to be operating The LOCKED signal of the DCM can be used to keep other components a reset state until the DCM is ready A custom core has been created that helps accomplish this It can be found in pc 532 labs User Area lab5 Copy the clk align core into the system s pcores directory Restart the EDK and add the core 8 Add an instance of the clk align core to the system and add all of its ports Connect the ports with the internal connections that follow external clk extend dcm reset dcm0 locked dcm1 locked fpga reset dcm reset sys clk predcm sys rst preclkalign zbt dcm locked opb dcm locked sys rst s dcm rst 9 Locate the system port that connects the external sys rst pin to the sys rst s net Alter it so that it connects to the sys rst preclkalign net 10 The system is now ready to be built and downloaded Be aware that Base System Builder connected the system reset signal to User Switch SW0 on the Multimedia board It is best to download the system with the switch in the reset state However the signal must be low in order for XMD to connect to the MicroBlaze 11 Do a quick sanity check by running XMD and doing a memory read and a memory write to the address space associated with the ZBT The address space associated with the ZBT is not the same as the address space associated with the EMC To find the address space check the Parameters tab of Add Edit Cores and select the instance of the opb emc 12 Run the sample application for another quick test of the ZBT memory communications Connecting Multiple ZBT banks One solution to connect multiple external memory banks is to use multiple EMCs However this is a significant waste of FPGA logic since as mentioned earlier an EMC is capable of controlling up to 8 external banks We will now use an EMC to