ECE 532S Digital Hardware Voice Over IP Group Project Report Group members Leonard Siu Wendy Cheung Due date April 12 2004 Overview This project is a hardware client prototype for an existing Voice over IP VoIP system called Vocal Village1 The block diagram of the system is shown in Figure 1 FPGA To From Vocal Village Server Ethernet MAC controller Xilinx IP Ethernet Device audio in AC97 Codec AC97 Contoller Ethernet driver Xilinx driver MicroBlaze Softw are LWIP 3rd party Async FIFO Xilinx IP OPB Format converter Timer Xilinx IP UART Xilinx IP Sync FIFO Xilinx IP Interrupt Controller Xilinx IP Debug module Xilinx IP System OPB Interrupt driver Xilinx driver External Memory Controller Xilinx IP Digital Clock Manager DCM ZBT External Memory Figure 1 System block diagram The initial goal for the project is to establish a bi directional audio channel that communicates with the Vocal Village server through the Internet Protocol As the project 1 http www vocalvillage net progressed due to time constraints the aim was modified to doing uni directional communication as drawn in Figure 1 The audio input comes from a microphone connected to the Xilinx board The AC97 Codec on the board converts this analog signal to digital The AC97 controller configures the Codec and extracts the audio data Further processing includes bringing the data to the OPB clock domain converting it to a format that matches with the OPB width and storing it in a FIFO that can be accessed through the OPB The AC97 controller also has an OPB interface since it starts its operation when it gets signalled by the MicroBlaze processor In the audio data path system the FIFO blocks one asynchronous and one synchronous are IPs available from Xilinx The other cores were created The networking components include an EMAC controller Xilinx IP which interfaces with the Ethernet device used to interface with the Vocal Village server Xilinx also provides a driver for this controller Other Xilinx IP included in the system are a Timer and an Interrupt Controller which also have Xilinx drivers These components are used to call a function in the Light Weight Internet Protocol LWIP every 100ms which is required for the networking library to function properly ZBT Zero Bus Turnaround external memory was used for since the combine executable and library code is greater than the allow 64kb available with on chip BRAM To access this memory an External Memory Controller EMC which is Xilinx IP is used A Digital Clock Manager DCM block is used to synchronize the FPGA s internal logic and clock with the external memory s logic and clock In addition a 3rd party library called LWIP was used This library provided the client networking functionalities that is not available on the LibXil Net library from Xilinx Audio Data Path System The block diagram for the audio data path system is shown in Figure 2 On one end of the data path it takes audio input from a microphone Through several processing stages the data gets stored in a FIFO that s mapped to the OPB so that the data can be read by an OPB master such as the MicroBlaze processor FPGA Audio Bit Clk 12 288MHz Controller Bit Clk Mic Sdata In input AC97 Codec Sync OPB Clk 50MHz Wrapper Ctrl Sdata Out wr data wr en full OPB Slave Wrapper 32 bits 16 AC97 Read FIFO 16 bits 16 Async FIFO rd data rd en empty 32 wr data Sync wr en Format converter 15 entries FIFO full OPB Slave Attachment Attachment OPB MicroBlaze Processor Figure 2 Audio data path block diagram 32 entries IP Blocks Audio Controller Wrapper Functional Description On the Xilinx Multimedia board audio processing is done through the National Semiconductor LM4549 audio Codec2 This Codec is compliant with the specification for PC audio known as AC97 The Codec uses 18 bit ADC and DAC to convert between analog and digital signals and it can also mix and process the audio signals The role of the AC97 controller is to interface with the Codec so that input audio signals can be exchanged between the FPGA chip and the outside world The digital controller needs to generate a SYNC signal for the Codec to define the boundaries of each frame of audio data Each frame consists of 1 Tag Slot and 12 Data Slots As a 2 channel Codec it uses only 2 of the Data Slots for audio data one for the left channel and one for the right The AC97 controller extracts these 2 audio data samples from the serial input line SDATA IN packs them to 16 bit signals and stores them in an asynchronous FIFO The Tag Slot and 2 other Data Slots contain Codec status information and data read from a register In this implementation of the controller this data is not used thus it is ignored The rest of the slots are stuffed with zero so the controller doesn t look at those data bits too The Codec is configured by setting the values of its registers the output volume input volume and ADC sources are examples of options that can be set To write to a register the register address and the data to be written are embedded in the serial data SDATA OUT that the controller sends to the Codec The AC97 controller wrapper also interfaces with the OPB with a slave attachment The purpose of this is to allow the MicroBlaze processor to write to the memory mapped START register to signal the AC97 controller to start its operation of configuring the Codec and to subsequently start taking input data recorded from the microphone 2 The Codec s data sheet can be found at http cache national com ds LM LM4549A pdf which also describes the AC97 data format Interface Signals The Codec has 5 signals that are connected to the pins of the FPGA chip on the board BIT CLK SYNC SDATA IN SDATA OUT and PC BEEP The PC BEEP signal is an input to the Codec that can be mixed to both channels of a stereo signal It is not used in this project thus only the other 4 signals form the interface between the AC97 controller and the Codec BIT CLK is a 12 288MHz clock that s sent to the AC97 controller It s the clock for the serial input data to the controller SDATA IN and output data from the controller SDATA OUT The SYNC signal is generated by the AC97 controller and sent to the Codec to indicate the frame boundaries of the data The controller packs the audio samples extracted from SDATA IN and writes them to the asynchronous FIFO The interface between the controller and the FIFO is a standard write FIFO interface The controller sends a write enable signal and write data to the FIFO and the FIFO sends a full signal to the