Carnegie Mellon Virtual Memory Systems 15 213 Introduction to Computer Systems 16th Lecture Oct 19 2010 Instructors Randy Bryant and Dave O Hallaron 1 Carnegie Mellon Today Simple memory system example Case study Core i7 Linux memory system Memory mapping 2 Carnegie Mellon Review of Symbols Basic Parameters N 2n Number of addresses in virtual address space M 2m Number of addresses in physical address space P 2p Page size bytes Components of the virtual address VA TLBI TLB index TLBT TLB tag VPO Virtual page offset VPN Virtual page number Components of the physical address PA PPO Physical page offset same as VPO PPN Physical page number CO Byte offset within cache line CI Cache index CT Cache tag 3 Carnegie Mellon Simple Memory System Example Addressing 14 bit virtual addresses 12 bit physical address Page size 64 bytes 13 12 11 10 9 8 7 6 5 4 3 2 1 VPN VPO Virtual Page Number Virtual Page Offset 11 10 9 8 7 6 5 4 3 2 1 PPN PPO Physical Page Number Physical Page Offset 0 0 4 Carnegie Mellon Simple Memory System Page Table Only show first 16 entries out of 256 VPN PPN Valid VPN PPN Valid 00 28 1 08 13 1 01 0 09 17 1 02 33 1 0A 09 1 03 02 1 0B 0 04 0 0C 0 05 16 1 0D 2D 1 06 0 0E 11 1 07 0 0F 0D 1 5 Carnegie Mellon Simple Memory System TLB 16 entries 4 way associative TLBT 13 12 11 10 TLBI 9 8 7 6 5 4 3 VPN 2 1 0 VPO Set Tag PPN Valid Tag PPN Valid Tag PPN Valid Tag PPN Valid 0 03 0 09 0D 1 00 0 07 02 1 1 03 2D 1 02 0 04 0 0A 0 2 02 0 08 0 06 0 03 0 3 07 0 03 0D 1 0A 34 1 02 0 6 Carnegie Mellon Simple Memory System Cache 16 lines 4 byte block size Physically addressed Direct mapped CT 11 10 9 CI 8 7 6 5 4 CO 3 PPN 2 1 0 PPO Idx Tag Valid B0 B1 B2 B3 Idx Tag Valid B0 B1 B2 B3 0 19 1 99 11 23 11 8 24 1 3A 00 51 89 1 15 0 9 2D 0 2 1B 1 00 02 04 08 A 2D 1 93 15 DA 3B 3 36 0 B 0B 0 4 32 1 43 6D 8F 09 C 12 0 5 0D 1 36 72 F0 1D D 16 1 04 96 34 15 6 31 0 E 13 1 83 77 1B D3 7 16 1 11 C2 DF 03 F 14 0 7 Carnegie Mellon Address Translation Example 1 Virtual Address 0x03D4 TLBT TLBI 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 VPN 0x0F VPN VPO 0x3 TLBI 0x03 TLBT Physical Address Y TLB Hit Page Fault 0x0D PPN CI CT CO 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 1 0 0 PPN 0 N 0x5 0x0D PPO Y 0x36 8 Carnegie Mellon Address Translation Example 2 Virtual Address 0x0B8F TLBT TLBI 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0 0 0 1 1 1 1 VPN 0x2E VPN VPO 2 TLBI 0x0B TLBT Physical Address 11 N TLB Hit Y Page Fault 9 PPN PPN CI CT 10 TBD 8 7 6 5 4 CO 3 2 1 0 PPO 9 Carnegie Mellon Address Translation Example 3 Virtual Address 0x0020 TLBT TLBI 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 VPN 0x00 VPN VPO 0 TLBI 0x00 TLBT Physical Address N TLB Hit Page Fault 0x28 PPN CI CT CO 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 0 0 1 0 0 0 0 0 PPN 0 N 0x8 0x28 PPO N Mem 10 Carnegie Mellon Today Simple memory system example Case study Core i7 Linux memory system Memory mapping 11 Carnegie Mellon Intel Core i7 Memory System Processor package Core x4 Registers Registers Instruction Instruction fetch fetch L1 L1 d cache d cache 32 32 KB KB 8 way 8 way L1 L1 i cache i cache 32 32 KB KB 8 way 8 way L2 L2 unified unified cache cache 256 256 KB KB 8 way 8 way MMU MMU addr addr translation translation L1 L1 d TLB d TLB 64 64 entries entries 4 way 4 way L1 L1 i TLB i TLB 128 128 entries entries 4 way 4 way L2 L2 unified unified TLB TLB 512 512 entries entries 4 way 4 way QuickPath QuickPath interconnect interconnect 44 links links 25 6 25 6 GB s GB s each each L3 L3 unified unified cache cache 88 MB MB 16 way 16 way shared shared by by all all cores cores To other cores To I O bridge DDR3 DDR3 Memory Memory controller controller 33 xx 64 64 bit bit 10 66 10 66 GB s GB s 32 32 GB s GB s total total shared shared by by all all cores cores Main Main memory memory 12 Carnegie Mellon Review of Symbols Basic Parameters N 2n Number of addresses in virtual address space M 2m Number of addresses in physical address space P 2p Page size bytes Components of the virtual address VA TLBI TLB index TLBT TLB tag VPO Virtual page offset VPN Virtual page number Components of the physical address PA PPO Physical page offset same as VPO PPN Physical page number CO Byte offset within cache line CI Cache index CT Cache tag 13 Carnegie Mellon End to end Core i7 Address Translation 32 64 CPU L2 L3 and main memory Result Virtual address VA 36 12 VPN VPO 32 L1 miss L1 hit 4 TLBT TLBI L1 d cache 64 sets 8 lines set TLB hit TLB miss L1 TLB 16 sets 4 entries set 9 9 9 9 40 VPN1 VPN2 VPN3 VPN4 PPN CR3 PTE PTE PTE Page tables PTE 12 40 6 6 PPO CT CI CO Physical address PA 14 Carnegie Mellon Core i7 Level 1 3 Page Table Entries 63 62 XD 52 51 Unused 12 11 9 Page table physical base address Unused 8 G 7 PS 6 5 A 4 3 2 1 0 CD WT U S R W P 1 Available for OS page table location on disk P 0 Each entry references a 4K child page table P Child page table present in physical memory 1 or not 0 R W Read only or read write access access permission for all reachable pages U S user or supervisor kernel mode access permission for all reachable pages WT Write through or write …
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