•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IL06: Complementary CMOS Logic GatesDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F9/14/2005 VLSI Design I; A. Milenkovic 2Course Administration• Instructor: Aleksandar [email protected]/~milenkaEB 217-LMon. 5:30 PM – 6:30 PM, Wen. 12:30 – 13:30 PM • URL: http://www.ece.uah.edu/~milenka/cpe527-05F• TA: Joel Wilder• Labs: Lab#2 posted (due 9/23/05)• Text: CMOS VLSI Design, 3rded., Weste, Harris• Review: Introduction, Design Metrics, IC Fabrication (Read Chapter 1); IC Fabrication (Chapter 3)• Today: MOS Non-ideal IV, CMOS Inverter (Chapter 2)9/14/2005 VLSI Design I; A. Milenkovic 3CMOS Inverter VTC00.511.522.500.511.522.5Vin(V)Vout(V)NMOS offPMOS resNMOS satPMOS resNMOS satPMOS satNMOS resPMOS satNMOS resPMOS off00.511.522.500.511.522.5Vin(V)Vout(V)NMOS offPMOS resNMOS satPMOS resNMOS satPMOS satNMOS resPMOS satNMOS resPMOS off9/14/2005 VLSI Design I; A. Milenkovic 4Beta Ratio• If βp/ βn≠ 1, switching point will move from VDD/2• Called skewed gate• Other gates: collapse into equivalent inverterVout0VinVDDVDD0.51210pnββ=0.1pnββ=9/14/2005 VLSI Design I; A. Milenkovic 5Noise Margins• How much noise can a gate input see before it does not recognize the input?IndeterminateRegionNMLNMHInput CharacteristicsOutput CharacteristicsVOHVDDVOLGNDVIHVILLogical HighInput RangeLogical LowInput RangeLogical HighOutput RangeLogical LowOutput Range9/14/2005 VLSI Design I; A. Milenkovic 6Logic Levels• To maximize noise margins, select logic levels at VDDVinVoutVDDβp/βn > 1VinVout0•VLSI Design I; A. Milenkovic •29/14/2005 VLSI Design I; A. Milenkovic 7Logic Levels• To maximize noise margins, select logic levels at – unity gain point of DC transfer characteristicVDDVinVoutVOHVDDVOLVILVIHVtnUnity Gain PointsSlope = -1VDD-|Vtp|βp/βn > 1VinVout09/14/2005 VLSI Design I; A. Milenkovic 8CMOS Inverter: Switch Model of Dynamic BehaviorVDDRnVoutCLVin= VDDVDDRpVoutCLVin= 09/14/2005 VLSI Design I; A. Milenkovic 9CMOS Inverter: Switch Model of Dynamic BehaviorVDDRnVoutCLVin= VDDVDDRpVoutCLVin= 0Gate response time is determined by the time to charge CLthrough Rp(discharge CLthrough Rn)9/14/2005 VLSI Design I; A. Milenkovic 10Relative Transistor Sizing • When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to– maximize the noise margins and– obtain symmetrical characteristics9/14/2005 VLSI Design I; A. Milenkovic 11Switching Threshold•VMwhere Vin= Vout(both PMOS and NMOS in saturation since VDS= VGS)VM≈ rVDD/(1 + r) where r = kpVDSATp/knVDSATn• Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors• Want VM= VDD/2 (to have comparable high and low noise margins), so want r ≈ 1 (W/L)pkn’VDSATn(VM-VTn-VDSATn/2)(W/L)nkp’VDSATp(VDD-VM+VTp+VDSATp/2)=9/14/2005 VLSI Design I; A. Milenkovic 12Switch Threshold Example• In our generic 0.25 micron CMOS process, using the process parameters from slide L03.25, a VDD= 2.5V, and a minimum size NMOS device ((W/L)nof 1.5)-0.1-30 x 10-6-1-0.4-0.4PMOS0.06115 x 10-60.630.40.43NMOSλ(V-1)k’(A/V2)VDSAT(V)γ(V0.5)VT0(V)(W/L)p(W/L)n =•VLSI Design I; A. Milenkovic •39/14/2005 VLSI Design I; A. Milenkovic 13Switch Threshold Example• In our generic 0.25 micron CMOS process, using the process parameters, a VDD= 2.5V, and a minimum size NMOS device ((W/L)nof 1.5)-0.1-30 x 10-6-1-0.4-0.4PMOS0.06115 x 10-60.630.40.43NMOSλ(V-1)k’(A/V2)VDSAT(V)γ(V0.5)VT0(V)(W/L)p115 x 10-60.63 (1.25 – 0.43 – 0.63/2) (W/L)n -30 x 10-6 -1.0 (1.25 – 0.4 – 1.0/2)=xx= 3.5(W/L)p = 3.5 x 1.5 = 5.25 for a VMof 1.25V9/14/2005 VLSI Design I; A. Milenkovic 14Simulated Inverter VM0.80.911.11.21.31.41.50110(W/L)p/(W/L)nVM(V) VMis relatively insensitive to variations in device ratioz setting the ratio to 3, 2.5 and 2 gives VM’s of 1.22V, 1.18V, and 1.13V Increasing the width of the PMOS moves VMtowards VDD Increasing the width of the NMOS moves VMtoward GND.1Note: x-axis is semilog~3.49/14/2005 VLSI Design I; A. Milenkovic 15Noise Margins Determining VIHand VIL0123VIL VIHVinVoutVOH= VDDVMBy definition, VIHand VILare where dVout/dVin= -1 (= gain)VOL= GNDA piece-wise linear approximation of VTCNMH = VDD -VIHNML = VIL -GNDApproximating: VIH = VM -VM /gVIL = VM + (VDD -VM )/gSo high gain in the transition region is very desirable9/14/2005 VLSI Design I; A. Milenkovic 16CMOS Inverter VTC from Simulation00.511.522.500.511.522.5Vin(V)Vout(V)0.25um, (W/L)p/(W/L)n= 3.4(W/L)n= 1.5 (min size)VDD= 2.5VVM≈ 1.25V, g = -27.5VIL= 1.2V, VIH= 1.3VNML= NMH= 1.2(actual values are VIL= 1.03V, VIH= 1.45VNML= 1.03V & NMH= 1.05V)Output resistance low-output = 2.4kΩhigh-output = 3.3kΩ9/14/2005 VLSI Design I; A. Milenkovic 17Gain Determinates-18-16-14-12-10-8-6-4-2000.511.52VingainGain is a strong function of the slopes of the currents in the saturation region, for Vin= VM(1+r)g ≈ ----------------------------------(VM-VTn-VDSATn/2)(λn - λp )Determined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and VM(transistor sizing).9/14/2005 VLSI Design I; A. Milenkovic 18Impact of Process Variation on VTC Curve00.511.522.500.511.522.5Vin(V)Vout(V)NominalGood PMOSBad NMOSBad PMOSGood NMOSprocess variations (mostly) cause a shift in the switching threshold•VLSI Design I; A. Milenkovic •49/14/2005 VLSI Design I; A. Milenkovic 19Scaling the Supply Voltage00.511.522.500.5 11.5 22.5Vin(V)Vout(V)Device threshold voltages are kept (virtually) constant00.050.10.150.20 0.05 0.1 0.15 0.2Vin(V)Vout(V)Gain=-1Device threshold voltages are kept (virtually) constantStatic CMOS Logic9/14/2005 VLSI Design I; A. Milenkovic 21CMOS Circuit Styles• Static complementary CMOS - except during switching, output connected to either VDD or GND via a low-resistance path– high noise margins• full rail to rail swing• VOH and VOL are at VDD and GND, respectively– low output impedance, high input impedance– no steady state path between VDD and GND (no static power consumption)– delay a function of load capacitance and transistor resistance– comparable rise