•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IL19: Circuit FamiliesSequential CircuitsDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F10/31/2005 VLSI Design I; A. Milenkovic 2Outline• Pseudo-nMOS Logic• Dynamic Logic• Pass Transistor Logic10/31/2005 VLSI Design I; A. Milenkovic 3Review: Pseudo-nMOS• In the old days, nMOS processes had no pMOS– Instead, use pull-up transistor that is always ON• In CMOS, use a pMOS that is always ON– Ratio issue– Make pMOS about ¼ effective strength of pulldownnetworkVoutVin16/2P/2Idsload0 0.3 0.6 0.9 1.2 1.5 1.800.30.60.91.21.51.8P = 24P = 4P = 14VinVout10/31/2005 VLSI Design I; A. Milenkovic 4Review: Pseudo-nMOS Gates• Design for unit current on outputto compare with unit inverter.• pMOS fights nMOSInverter NAND2 NOR24/32/3AY8/38/32/3BAYAB4/34/32/3gu = 4/3gd = 4/9gavg = 8/9pu = 6/3pd = 6/9pavg = 12/9Ygu = 8/3gd = 8/9gavg = 16/9pu = 10/3pd = 10/9pavg = 20/9gu = 4/3gd = 4/9gavg = 8/9pu = 10/3pd = 10/9pavg = 20/9finputsY10/31/2005 VLSI Design I; A. Milenkovic 5Review: Pseudo-nMOS Power• Pseudo-nMOS draws power whenever Y = 0– Called static power P = I•VDD– A few mA / gate * 1M gates would be a problem– This is why nMOS went extinct!• Use pseudo-nMOS sparingly for wide NORs• Turn off pMOS when not in useABYCen10/31/2005 VLSI Design I; A. Milenkovic 6Review: Dynamic Logic• Dynamic gates uses a clocked pMOS pullup• Two modes: precharge and evaluate12AY4/32/3AY11AYφStatic Pseudo-nMOS Dynamicφ Precharge EvaluateYPrecharge•VLSI Design I; A. Milenkovic •210/31/2005 VLSI Design I; A. Milenkovic 7Review: Logical EffortInverter NAND2 NOR211AY221BAYAB111gd = 1/3pd = 2/3gd = 2/3pd = 3/3gd = 1/3pd = 3/3Yφφφ21AY331BAYAB221gd = 2/3pd = 3/3gd = 3/3pd = 4/3gd = 2/3pd = 5/3Yφφφfootedunfooted32210/31/2005 VLSI Design I; A. Milenkovic 8Monotonicity• Dynamic gates require monotonically rising inputs during evaluation–0 -> 0–0 -> 1–1 -> 1– But not 1 -> 0φ Precharge EvaluateYPrechargeAOutput should rise but does notviolates monotonicity during evaluationAφ10/31/2005 VLSI Design I; A. Milenkovic 9Monotonicity Woes• But dynamic gates produce monotonically falling outputs during evaluation• Illegal for one dynamic gate to drive another!AXφYφ Precharge EvaluateXPrechargeA = 1Y10/31/2005 VLSI Design I; A. Milenkovic 10Monotonicity Woes• But dynamic gates produce monotonically falling outputs during evaluation• Illegal for one dynamic gate to drive another!AXφYφ Precharge EvaluateXPrechargeA = 1Y should rise but cannotYX monotonically falls during evaluation10/31/2005 VLSI Design I; A. Milenkovic 11Domino Gates• Follow dynamic stage with inverting static gate– Dynamic / static pair is called domino gate– Produces monotonic outputsφ Precharge EvaluateWPrechargeXYZAφBCφφφCABWXYZ=XZHHAWφB CXYZdomino ANDdynamicNANDstaticinverter10/31/2005 VLSI Design I; A. Milenkovic 12Domino Optimizations• Each domino gate triggers next one, like a string of dominos toppling over• Gates evaluate sequentially but precharge in parallel• Thus evaluation is more critical than precharge• HI-skewed static stages can perform logicS0D0S1D1S2D2S3D3φS4D4S5D5S6D6S7D7φYH•VLSI Design I; A. Milenkovic •310/31/2005 VLSI Design I; A. Milenkovic 13Dual-Rail Domino• Domino only performs noninverting functions:– AND, OR but not NAND, NOR, or XOR• Dual-rail domino solves this problem– Takes true and complementary inputs – Produces true and complementary outputsinvalid11‘1’01‘0’10Precharged00Meaningsig_lsig_hY_hfφφinputsY_lf10/31/2005 VLSI Design I; A. Milenkovic 14Example: AND/NAND• Given A_h, A_l, B_h, B_l• Compute Y_h = A * B, Y_l = ~(A * B)10/31/2005 VLSI Design I; A. Milenkovic 15Example: AND/NAND• Given A_h, A_l, B_h, B_l• Compute Y_h = A * B, Y_l = ~(A * B)• Pulldown networks are conduction complementsY_hφφY_lA_hB_hB_lA_l= A*B= A*B10/31/2005 VLSI Design I; A. Milenkovic 16Example: XOR/XNOR• Sometimes possible to share transistorsY_hφφY_lA_lB_h= A xor BB_lA_hA_lA_h= A xnor B10/31/2005 VLSI Design I; A. Milenkovic 17Leakage• Dynamic node floats high during evaluation– Transistors are leaky (IOFF≠ 0)– Dynamic value will leak away over time– Formerly miliseconds, now nanoseconds!• Use keeper to hold dynamic node– Must be weak enough not to fight evaluationAφH221kXYweak keeper10/31/2005 VLSI Design I; A. Milenkovic 18Charge Sharing• Dynamic gates suffer from charge sharingB = 0AYφxCxCYAφxY•VLSI Design I; A. Milenkovic •410/31/2005 VLSI Design I; A. Milenkovic 19Charge Sharing• Dynamic gates suffer from charge sharingB = 0AYφxCxCYAφxYCharge sharing noisexYVV==10/31/2005 VLSI Design I; A. Milenkovic 20Charge Sharing• Dynamic gates suffer from charge sharingB = 0AYφxCxCYAφxYCharge sharing noiseYxY DDxYCVV VCC==+10/31/2005 VLSI Design I; A. Milenkovic 21Secondary Precharge• Solution: add secondary precharge transistors– Typically need to precharge every other node• Big load capacitance CYhelps as wellBAYφxsecondaryprechargetransistor10/31/2005 VLSI Design I; A. Milenkovic 22Noise Sensitivity• Dynamic gates are very sensitive to noise– Inputs: VIH≈ Vtn– Outputs: floating output susceptible noise• Noise sources– Capacitive crosstalk– Charge sharing– Power supply noise– Feedthrough noise–And more!10/31/2005 VLSI Design I; A. Milenkovic 23Domino Summary• Domino logic is attractive for high-speed circuits– 1.5 – 2x faster than static CMOS– But many challenges:• Monotonicity• Leakage• Charge sharing•Noise• Widely used in high-performance microprocessors10/31/2005 VLSI Design I; A. Milenkovic 24NMOS Transistors in Series/Parallel• Primary inputs drive both gate and source/drain terminals• NMOS switch closes when the gate input is high• Remember –NMOS transistors pass a strong 0 but a weak 1ABXYX = Y if A and BXYABX = Y if A or B•VLSI Design I; A. Milenkovic •510/31/2005 VLSI Design I; A. Milenkovic 25PMOS Transistors in Series/Parallel• Primary inputs drive both gate and source/drain terminals• PMOS switch closes when the gate input is low• Remember –PMOS transistors pass a strong 1 but a weak 0ABXYX = Y if A and B = A + BXYABX = Y if A or B = A •
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