•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IL11: Logical EffortDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F10/3/2005 VLSI Design I; A. Milenkovic 2Course Administration• Instructor: Aleksandar [email protected]/~milenkaEB 217-LMon. 5:30 PM – 6:30 PM, Wen. 12:30 – 13:30 PM • URL: http://www.ece.uah.edu/~milenka/cpe527-05F• TA: Joel Wilder• Labs: Lab#3: due 10/07/05• Hws: Solutions in secure directory /scr (cpe427fall05, ?)• Project: Proposals due 10/10/05• Test I: 10/17/05• Text: CMOS VLSI Design, 3rd ed., Weste, Harris• Review: Chapters 1, 2, 3, 4;• Today: Logical Effort (Chapter 4)10/3/2005 VLSI Design I; A. Milenkovic 3Outline• Introduction• Delay in a Logic Gate• Multistage Logic Networks• Choosing the Best Number of Stages•Example• Summary10/3/2005 VLSI Design I; A. Milenkovic 4Introduction• Chip designers face a bewildering array of choices– What is the best circuit topology for a function?– How many stages of logic give least delay?– How wide should the transistors be?• Logical effort is a method to make these decisions– Uses a simple model of delay– Allows back-of-the-envelope calculations– Helps make rapid comparisons between alternatives– Emphasizes remarkable symmetries? ? ?10/3/2005 VLSI Design I; A. Milenkovic 5Example• Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file.• Decoder specifications:– 16 word register file– Each word is 32 bits wide– Each bit presents load of 3 unit-sized transistors– True and complementary address inputs A[3:0]– Each input may drive 10 unit-sized transistors• Ben needs to decide:– How many stages to use?– How large should each gate be?– How fast can decoder operate?A[3:0] A[3:0]1632 bits16 words4:16 DecoderRegister File10/3/2005 VLSI Design I; A. Milenkovic 6Delay in a Logic Gate• Express delays in process-independent unitabsddτ=τ = 3RC≈ 12 ps in 180 nm process40 ps in 0.6 µm process•VLSI Design I; A. Milenkovic •210/3/2005 VLSI Design I; A. Milenkovic 7Delay in a Logic Gate• Express delays in process-independent unit• Delay has two componentsabsddτ=dfp=+10/3/2005 VLSI Design I; A. Milenkovic 8Delay in a Logic Gate• Express delays in process-independent unit• Delay has two components• Effort delay f = gh (a.k.a. stage effort)– Again has two componentsabsddτ=dpf=+10/3/2005 VLSI Design I; A. Milenkovic 9Delay in a Logic Gate• Express delays in process-independent unit• Delay has two components• Effort delay f = gh (a.k.a. stage effort)– Again has two components• g: logical effort– Measures relative ability of gate to deliver current– g ≡ 1 for inverterabsddτ=dfp=+10/3/2005 VLSI Design I; A. Milenkovic 10Delay in a Logic Gate• Express delays in process-independent unit• Delay has two components• Effort delay f = gh (a.k.a. stage effort)– Again has two components• h: electrical effort = Cout/ Cin– Ratio of output to input capacitance– Sometimes called fanoutabsddτ=dfp=+10/3/2005 VLSI Design I; A. Milenkovic 11Delay in a Logic Gate• Express delays in process-independent unit• Delay has two components• Parasitic delay p– Represents delay of gate driving no load– Set by internal parasitic capacitanceabsddτ=dpf=+10/3/2005 VLSI Design I; A. Milenkovic 12Delay Plotsd = f + p= gh + pElectrical Ef f o r t:h = Cout / CinNormalized Delay: dInv er ter2-inputNANDg =p =d =g =p =d =0123450123456•VLSI Design I; A. Milenkovic •310/3/2005 VLSI Design I; A. Milenkovic 13Delay Plotsd = f + p= gh + p• What about NOR2?Electrical Ef f o r t:h = Cout / CinNormalized Delay: dInv er ter2-inputNANDg = 1p = 1d = h + 1g = 4/3p = 2d = (4/3)h + 2Ef f o r t Delay : fParasitic Delay: p012345012345610/3/2005 VLSI Design I; A. Milenkovic 14Computing Logical Effort• DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.• Measure from delay vs. fanout plots• Or estimate by counting transistor widthsAYABYABY1211222244Cin = 3g = 3/3Cin = 4g = 4/3Cin = 5g = 5/310/3/2005 VLSI Design I; A. Milenkovic 15Catalog of Gates8, 16, 16, 86, 12, 64, 4XOR, XNOR22222Tristate / mux(2n+1)/39/37/35/3NOR(n+2)/36/35/34/3NAND1Invertern4321Number of inputsGate type• Logical effort of common gates10/3/2005 VLSI Design I; A. Milenkovic 16Catalog of Gates864XOR, XNOR2n8642Tristate / muxn432NORn432NAND1Invertern4321Number of inputsGate type• Parasitic delay of common gates– In multiples of pinv(≈1)10/3/2005 VLSI Design I; A. Milenkovic 17Example: Ring Oscillator• Estimate the frequency of an N-stage ring oscillatorLogical Effort: g = Electrical Effort: h =Parasitic Delay: p =Stage Delay: d =Frequency: fosc= 10/3/2005 VLSI Design I; A. Milenkovic 18Example: Ring Oscillator• Estimate the frequency of an N-stage ring oscillatorLogical Effort: g = 1Electrical Effort: h = 1Parasitic Delay: p = 1Stage Delay: d = 2Frequency: fosc= 1/(2*N*d) = 1/4N31 stage ring oscillator in 0.6 µm process has frequency of ~ 200 MHz•VLSI Design I; A. Milenkovic •410/3/2005 VLSI Design I; A. Milenkovic 19Example: FO4 Inverter• Estimate the delay of a fanout-of-4 (FO4) inverterLogical Effort: g = Electrical Effort: h =Parasitic Delay: p =Stage Delay: d =d10/3/2005 VLSI Design I; A. Milenkovic 20Example: FO4 Inverter• Estimate the delay of a fanout-of-4 (FO4) inverterLogical Effort: g = 1Electrical Effort: h = 4Parasitic Delay: p = 1Stage Delay: d = 5dThe FO4 delay is about200 ps in 0.6 µm process60 ps in a 180 nm processf/3 ns in an f µm process10/3/2005 VLSI Design I; A. Milenkovic 21Multistage Logic Networks• Logical effort generalizes to multistage networks• Path Logical Effort• Path Electrical Effort• Path EffortiGg=∏out-pathin-pathCHC=iiiFfgh==∏∏10xyz20g1 = 1h1 = x/10g2 = 5/3h2 = y/xg3 = 4/3h3 = z/yg4 = 1h4 = 20/z10/3/2005 VLSI Design I; A. Milenkovic 22Multistage Logic Networks• Logical effort generalizes to multistage networks• Path Logical Effort• Path Electrical Effort• Path Effort• Can we write F = GH?iGg=∏out pathin pathCHC−−=iiiFfgh==∏∏10/3/2005 VLSI Design I; A. Milenkovic 23Paths that Branch• No! Consider paths that
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