UAH CPE 427 - Design Metrics and IC Manufacturing

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•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IL02: Design Metrics & IC ManufacturingDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F8/31/2005 VLSI Design I; A. Milenkovic 2Fundamental Design Metrics• Functionality•Cost– NRE (fixed) costs - design effort– RE (variable) costs - cost of parts, assembly, test• Reliability, robustness– Noise margins– Noise immunity• Performance– Speed (delay)– Power consumption; energy• Time-to-market•VLSI Design I; A. Milenkovic •28/31/2005 VLSI Design I; A. Milenkovic 3Cost of Integrated Circuits• NRE (non-recurring engineering) costs– Fixed cost to produce the design• design effort• design verification effort• mask generation– Influenced by the design complexity and designer productivity– More pronounced for small volume products• Recurring costs – proportional to product volume– silicon processing• also proportional to chip area– assembly (packaging)–testVolumecostFixedICpercostVariableICperCost +=8/31/2005 VLSI Design I; A. Milenkovic 4NRE Cost is Increasing•VLSI Design I; A. Milenkovic •38/31/2005 VLSI Design I; A. Milenkovic 5Cost per Transistor0.00000010.00000010.0000010.0000010.000010.000010.00010.00010.0010.0010.010.010.10.1111982198219851985198819881991199119941994199719972000200020032003200620062009200920122012cost: cost: ¢¢--perper--transistortransistorFabrication capital cost per transistor (Moore’s law)8/31/2005 VLSI Design I; A. Milenkovic 6Silicon WaferSingle dieWaferFrom http://www.amd.comGoing up to 12” (30cm)•VLSI Design I; A. Milenkovic •48/31/2005 VLSI Design I; A. Milenkovic 7Recurring CostsyieldtestFinalcostPackagingcostTestingcostDiecostVariable++=yieldDiewaferperDieswaferofCostdieofCost×=8/31/2005 VLSI Design I; A. Milenkovic 8Dies per WaferareaDie2diameterWaferπareaDie)diameter/2(WaferπwaferperDies2××−×=•VLSI Design I; A. Milenkovic •58/31/2005 VLSI Design I; A. Milenkovic 9YieldααareaDieareaunitperDefects1yieldWaferyieldDie−⎟⎠⎞⎜⎝⎛×+×=α is approximately 3 4area) (die cost die f=8/31/2005 VLSI Design I; A. Milenkovic 10Examples of Cost Metrics (1994)$4179%402961.5$15000.803Pentium$27213%482561.6$17000.703Super SPARC$14919%532341.2$15000.703DEC Alpha$7327%661961.0$13000.803HP PA 7100$5328%1151211.3$17000.804PowerPC 601$1254%181811.0$12000.803486DX2$471%360431.0$9000.902386DXDie costYieldDies/waferArea (mm2)Defects/cm2Wafer costLine widthMetal layersChip•VLSI Design I; A. Milenkovic •68/31/2005 VLSI Design I; A. Milenkovic 11Yield Example• Example #1: – 20-cm wafer for a die that is 1.5 cm on a side.– Solution: Die area = 1.5x1.5 = 2.25cm2. Dies per wafer = 3.14x(20/2)2/2.25 – 3.14x20/(2x2.5)0.5=110.•Example #2– wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,α = 3 (measure of manufacturing process complexity)– 252 dies/wafer (remember, wafers round & dies square)– die yield of 16%– 252 x 16% = only 40 dies/wafer die yield !• Die cost is strong function of die area– proportional to the third or fourth power of the die area8/31/2005 VLSI Design I; A. Milenkovic 12Functionality and Robustness• Prime requirement –IC performs the function it is designed for• Normal behavior deviatesdue to – variations in the manufacturing process (dimensions and device parameters vary between runs and even on a single wafer or die)– presence of disturbing on- or off-chip noise sources• Noise: Unwanted variation of voltages or currents at the logic nodes•VLSI Design I; A. Milenkovic •78/31/2005 VLSI Design I; A. Milenkovic 13Reliability Noise in Digital Integrated Circuitsi(t)Inductive coupling Capacitive coupling Power and groundnoisev(t)VDD• from two wires placed side by side– inductive coupling• current change on one wire caninfluence signal on the neighboring wire– capacitive coupling• voltage change on one wire can influence signal on the neighboring wire• cross talk• from noise on the power and ground supply rails– can influence signal levels in the gate8/31/2005 VLSI Design I; A. Milenkovic 14Example of Capacitive Coupling• Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scaleCrosstalk vs. Technology0.16m CMOS0.12m CMOS0.35m CMOS0.25m CMOSPulsed SignalBlack line quietRed lines pulsedGlitches strength vs technology From Dunlop, Lucent, 2000•VLSI Design I; A. Milenkovic •88/31/2005 VLSI Design I; A. Milenkovic 15Static Gate Behavior• Steady-state parameters of a gate – static behavior –tell how robust a circuit is with respect to both variations in the manufacturing process and to noise disturbances.• Digital circuits perform operations on Boolean variables x ∈{0,1}• A logical variable is associated with a nominal voltage level for each logic state1 ⇔ VOHand 0 ⇔ VOL• Difference between VOHand VOLis the logic or signal swing VswV(y)V(x)VOH = ! (VOL)VOL = ! (VOH)8/31/2005 VLSI Design I; A. Milenkovic 16DC OperationVoltage Transfer CharacteristicVOH= f(VOL)VOL= f(VOH)VM= f(VM)V(x)V(y)fV(y)V(x)VOH = f (VIL)VILVIHV(y)=V(x)Switching ThresholdVMVOL = f (VIH)•VLSI Design I; A. Milenkovic •98/31/2005 VLSI Design I; A. Milenkovic 17Mapping between analog and digital signals• The regions of acceptable high and low voltages are delimited byVIH and VIL that represent the points on the VTC curve where thegain = -1 (dVout/dVin)VILVIHVinSlope = -1Slope = -1VOLVOHVout“0”VOLVILVIHVOHUndefinedRegion“1”8/31/2005 VLSI Design I; A. Milenkovic 18Definition of Noise MarginsGate OutputGate Input Large noise margins are desirable, but not sufficient … For robust circuits, want the “0” and “1” intervals to be as large as possibleGndUndefinedRegion"1""0"VOHVILVOLVIHNoise Margin HighNoise Margin LowNMH = VOH-VIHNML = VIL-VOLVDDVDDGndGnd•VLSI Design I; A. Milenkovic •108/31/2005 VLSI Design I; A. Milenkovic 19The Regenerative Property• A gate with regenerative property ensure that a disturbed signal converges back to a nominal voltage levelv0v1v2v3v4v5v6-11350246810t (nsec)V (volts)v0v2v18/31/2005 VLSI Design I; A. Milenkovic 20Conditions for Regenerationv1= f(v0) ⇒ v1= finv(v2)v0v1v2v3v4v5v6v0v1v2v3f(v)finv(v)Regenerative Gatev0v1v2v3f(v)finv(v)Nonregenerative Gate To be


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