•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IL12: WiresDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F10/4/2005 VLSI Design I; A. Milenkovic 2Course Administration• Instructor: Aleksandar [email protected]/~milenkaEB 217-LMon. 5:30 PM – 6:30 PM, Wen. 12:30 – 13:30 PM • URL: http://www.ece.uah.edu/~milenka/cpe527-05F• TA: Joel Wilder• Labs: Lab#3: due 10/07/05• Hws: Solutions in secure directory /scr (cpe427fall05, ?)• Project: Proposals due 10/10/05• Test I: 10/17/05• Text: CMOS VLSI Design, 3rd ed., Weste, Harris• Review: Chapters 1, 2, 3, 4;• Today: Wires (Chapter 4)•VLSI Design I; A. Milenkovic •210/4/2005 VLSI Design I; A. Milenkovic 3REVIEW: FO4 Inverter• Estimate the delay of a fanout-of-4 (FO4) inverterLogical Effort: g = 1Electrical Effort: h = 4Parasitic Delay: p = 1Stage Delay: d = 5dThe FO4 delay is about200 ps in 0.6 µm process60 ps in a 180 nm processf/3 ns in an f µm process10/4/2005 VLSI Design I; A. Milenkovic 4REVIEW: Multistage Logic Networks• Logical effort generalizes to multistage networks• Path Logical Effort• Path Electrical Effort• Path EffortiGg=∏out-pathin-pathCHC=iiiFfgh==∏∏10xyz20g1 = 1h1 = x/10g2 = 5/3h2 = y/xg3 = 4/3h3 = z/yg4 = 1h4 = 20/z•VLSI Design I; A. Milenkovic •310/4/2005 VLSI Design I; A. Milenkovic 5REVIEW: Branching Effort• Introduce branching effort– Accounts for branching between stages in path• Now we compute the path effort– F = GBHon path off pathon pathCCbC+=iBb=∏ihBH=∏Note:10/4/2005 VLSI Design I; A. Milenkovic 6REVIEW: Multistage Delays• Path Effort Delay• Path Parasitic Delay• Path DelayFiDf=∑iPp=∑iFDdDP==+∑•VLSI Design I; A. Milenkovic •410/4/2005 VLSI Design I; A. Milenkovic 7REVIEW: Designing Fast Circuits• Delay is smallest when each stage bears same effort• Thus minimum delay of N stage path is• This is a key result of logical effort– Find fastest possible delay– Doesn’t require calculating gate sizesiFDdDP==+∑1ˆNiifghF==1NDNF P=+10/4/2005 VLSI Design I; A. Milenkovic 8REVIEW: Gate Sizes• How wide should the gates be for least delay?• Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives.• Check work by verifying input cap spec is met.ˆˆoutiniiCCioutinfghggCCf==⇒=•VLSI Design I; A. Milenkovic •510/4/2005 VLSI Design I; A. Milenkovic 9REVIEW: Best Number of Stages• How many stages should a path use?– Minimizing number of stages is not always fastest• Example: drive 64-bit datapath with unit inverterD =111164 64 64 64Initial Driv erDatapath LoadN:f:D:123410/4/2005 VLSI Design I; A. Milenkovic 10REVIEW: Best Number of Stages• How many stages should a path use?– Minimizing number of stages is not always fastest• Example: drive 64-bit datapath with unit inverterD = NF1/N+ P= N(64)1/N + N11118416 82.82364 64 64 64Initial Driv erDatapath LoadN:f:D:164652818341542.815.3Fastest•VLSI Design I; A. Milenkovic •610/4/2005 VLSI Design I; A. Milenkovic 11REVIEW: Derivation• Consider adding inverters to end of path– How many give least delay?• Define best stage effort N - n1 Ext r a Inverter sLogic Block:n1 StagesPath Ef f or t F()1111NniinviDNF p Nnp==++−∑111ln 0NNNinvDFFFpN∂=− + + =∂()1ln 0invpρρ+− =1NFρ=10/4/2005 VLSI Design I; A. Milenkovic 12Best Stage Effort• has no closed-form solution• Neglecting parasitics (pinv= 0), we find ρ = 2.718 (e)• For pinv= 1, solve numerically for ρ = 3.59()1ln 0invpρρ+− =•VLSI Design I; A. Milenkovic •710/4/2005 VLSI Design I; A. Milenkovic 13Sensitivity Analysis• How sensitive is delay to using exactly the best number of stages?• 2.4 < ρ < 6 gives delay within 15% of optimal– We can be sloppy!– I like ρ = 41.01.21.41.61.0 2.00.5 1.40.7N / N1.151.261.51(ρ =2.4)(ρ =6)D(N) /D(N)0.010/4/2005 VLSI Design I; A. Milenkovic 14Example, Revisited• Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file.• Decoder specifications:– 16 word register file– Each word is 32 bits wide– Each bit presents load of 3 unit-sized transistors– True and complementary address inputs A[3:0]– Each input may drive 10 unit-sized transistors• Ben needs to decide:– How many stages to use?– How large should each gate be?– How fast can decoder operate?A[3:0] A[3:0]1632 bits16 words4:16 DecoderRegister File•VLSI Design I; A. Milenkovic •810/4/2005 VLSI Design I; A. Milenkovic 15Number of Stages• Decoder effort is mainly electrical and branchingElectrical Effort: H =Branching Effort: B =• If we neglect logical effort (assume G = 1)Path Effort: F =Number of Stages: N =10/4/2005 VLSI Design I; A. Milenkovic 16Number of Stages• Decoder effort is mainly electrical and branchingElectrical Effort: H = (32*3) / 10 = 9.6Branching Effort: B = 8• If we neglect logical effort (assume G = 1)Path Effort: F = GBH = 76.8Number of Stages: N = log4F = 3.1• Try a 3-stage design•VLSI Design I; A. Milenkovic •910/4/2005 VLSI Design I; A. Milenkovic 17Gate Sizes & DelayLogical Effort: G =Path Effort: F =Stage Effort:Path Delay:Gate sizes: z = y =A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]word[0]word[15]96 units of wordline capacitance10 10 10 10 10 10 10 10yzyzˆf=D=10/4/2005 VLSI Design I; A. Milenkovic 18Gate Sizes & DelayLogical Effort: G = 1 * 6/3 * 1 = 2Path Effort: F = GBH = 154Stage Effort:Path Delay:Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]word[0]word[15]96 units of wordline capacitance10 10 10 10 10 10 10 10yzyz1/3ˆ5.36fF==ˆ3 1 4 1 22.1Df=+++=•VLSI Design I; A. Milenkovic •1010/4/2005 VLSI Design I; A. Milenkovic 19Comparison• Compare many alternatives with a spreadsheet21.6816/96NAND2-INV-NAND2-INV-INV-INV20.4716/95INV-NAND2-INV-NAND2-INV19.7616/94NAND2-INV-NAND2-INV20.5620/94NAND2-NOR2-INV-INV21.1724NAND4-INV-INV-INV22.1623INV-NAND4-INV30.1420/92NAND2-NOR229.8522NAND4-INVDPGNDesign10/4/2005 VLSI Design I; A. Milenkovic 20Review of Definitionsdelayparasitic delayeffort delayeffortbranching effortelectrical effortlogical effortnumber of stagesPathStageTermiGg=∏out-pathin-pathCCH =NiBb=∏FGBH=FiDf=∑iPp=∑iFDdDP==+∑outinCCh =on-path