1. INTRODUCTION 2. PREPARE THE CADENCE TOOLS 3. RTL SIMULATION 4. LOGIC SYNTHESIS 5. POST-SYNTHESIS VERIFICATION 6. AUTO PLACE AND ROUTE 7. IMPORT LAYOUT DESIGN INTO CADENCE VIRTUOSO AND SCHEMATIC TOOLS 8. ADD PADFRAME TO CORE 9. ASSIGNMENTCPE/EE 427, CPE 527, VLSI Design I: Tutorial #4, Standard cell design flow (from verilog to layout, 8-bit accumulator) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville Adapted Illinois Institute of Technology, Dept. of Electrical and Computer Engineering Author: Johannes Grad and James E. Stine 1. INTRODUCTION In this tutorial exercise you will create an 8-bit accumulator from a verilog file. You will perform RTL simulation on this design. Next, you will synthesize this design to provide a gate-level netlist, and you will simulate this post-synthesized design. Subsequently, you will use Encounter to perform an automatic place-and-route of your 8-bit accumulator. Next, you will perform verifications on this design by importing it into the Cadence icfb tool as a schematic and a routed design. After ensuring that your core design is correct, you will add a padframe to your core design and then repeat the workflow as given for the core: synthesize the design, simulate, place-and-route, and verification steps. This tutorial repeats the workflow from Tutorial 3, but for a verilog design process (instead of schematic capture), straight through to creating an ASIC chip ready for fabrication. You will base your design on the 0.5um AMI nwell process (lambda = 0.30um). 2. PREPARE THE CADENCE TOOLS From your home directory, change directories into your cadence working directory: % cd cadence Make a directory for lab4 and change into that directory: % mkdir lab4 % cd lab4 3. RTL SIMULATION Typically you enter code in Verilog on the Register-Transfer level (RTL), that is, you model your design using clocked registers, datapath elements and control elements. Download the following files into your lab4 directory: • accu_nopads.v - Verilog RTL code for an 8-bit accumulator, without pads • accu_pads.v – Verilog RTL code for an 8-bit accumulator, with pads • accu_test.v - Verilog testbench for accu_nopads.v and accu_pads.v Also make sure that you have “cds.lib” and “osu.lib” from the previous lab directory. Now use the following the command to initialize the libraries cp $CDK_DIR/cdssetup/cdsinit .cdsinitVLSI Design I, Tutorial 4 You’re going to work with the core design first (no pads). In order to simulate the Verilog code for this design, use this command at the Unix prompt ($): $verilog accu_nopads.v accu_test.v See Figure 1 for the output of this command. Figure 1. RTL Verilog simulation output text. This testbench provides results directly on the screen and also in a waveform database. From the screen you can see that the design behaves as expected. That is, every 10ns a “1” is added to the accumulator output. This is expected since in the testbench a clock of 10ns is specified and the input “in” is connected to a constant “1”. Now, you will use the program Cadence Simvision to look at the waveform database that was created by the verilog simulation. Type the following command at the unix prompt (this tool was used in Tutorial 3): $ simvision& Page 2 of 18VLSI Design I, Tutorial 4 (The “&” symbol tells the operating system to run the Simvision program in the background – relative to that terminal window.) In the Simvision Design Browser window, open the Waveform database by clicking on the “Open” symbol. Then double-click on “shm.db”, which is the folder where the file is located. Inside the folder is only one file, shm.trn. Double-click on the file to open it. To see the contents of the waveform database, click on “stimulus” in the scope tree (as shown in Figure 2). Figure 2. Design Browser window. Now, plot the waveforms as you did in Tutorial 3 (select all signals and send them to the waveform browser). You will see your output similar to Figure 3 (and similar to the accumulator you constructed in Tutorial 3 via schematic capture!). Verify that the accumulator is operating as expected. Page 3 of 18VLSI Design I, Tutorial 4 Figure 3. Simulation Results. 4. LOGIC SYNTHESIS Once you have verified that your Verilog RTL code is working correctly you can synthesize it into standard cells. The result will be a gate-level netlist that only contains interconnected standard cells. (In Tutorial 3 you created the gate-level netlist through schematic capture – you specified how the gates would be connected. Here, the RTL code specifies the functionality of the circuit, and then you use logic synthesis in order to transfer that functionality into a gate-level netlist. Using this Verilog workflow, you will observe that there are two levels of circuit optimization, meaning that you specify a target frequency to the logic synthesizer, and it works to achieve that target frequency by generating a gate-level netlist and then checking slack time to see if the data signal will arrive before the rising edge of the clock. The second level of optimization is through Encounter, which you dealt with in Tutorial 3 through the .sdc file, where you set the timing constraint for the clock and Encounter routes the design in order to achieve that frequency. The .sdc file is generated automatically through the logic synthesizer.) There are template files for all the following steps already prepared for you. You will now copy those templates into your project. To keep things organized you will run synthesis in a separate folder. That way it will be separate from the original RTL code. Use the mkdir command to create a folder. Then copy the templates, as shown below: $ mkdir encounter $ cd encounter $ cp /apps/iit_lib/osu/osu_stdcells/flow/ami05/* . $ cp /home/grad/wilderj/public_html/synopsys/* . (retrieves a script file and a library file) Now you have created the “encounter” folder and filled it with the template files for the AMI 0.5um technology. (identical to what was done in Tutorial 3) You will use the tool Synopsys Design Compiler for logic synthesis. The script file you’ll use with Synopsys is called “compile_dc.tcl”. This file is retrieved as shown above. Now you will open Page 4 of 18VLSI Design I, Tutorial 4 “compile_dc.tcl” in a text editor and modify it according to your accumulator design. This file is a