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•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IL20: Sequential CircuitsDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F11/1/2005 VLSI Design I; A. Milenkovic 2Review: Pass Transistor Circuits• Use pass transistors like switches to do logic• Inputs drive diffusion terminals as well as gates• CMOS + Transmission Gates:– 2-input multiplexer– Gates should be restoringABSSSYABSSSY11/1/2005 VLSI Design I; A. Milenkovic 3TG MultiplexerGNDVDDIn1In2SSS SSSSIn2In1FFF = !(In1 • S + In2• S) 11/1/2005 VLSI Design I; A. Milenkovic 4Transmission Gate XORBAA ⊕ B11/1/2005 VLSI Design I; A. Milenkovic 5Transmission Gate XORBAA ⊕ B1offoffan inverterB • !A0ononweak 0 if !Aweak 1 if AA • !B11/1/2005 VLSI Design I; A. Milenkovic 6TG Full AdderSumCoutABCin•VLSI Design I; A. Milenkovic •211/1/2005 VLSI Design I; A. Milenkovic 7Differential TG Logic (DPL)AABBBAND/NANDF=A⊕BF=A⊕BXOR/XNORAABBAABF=ABF=ABAABBA B AGNDGNDVDDVDDB11/1/2005 VLSI Design I; A. Milenkovic 8CPL• Complementary Pass-transistor Logic– Dual-rail form of pass transistor logic– Avoids need for ratioed feedback– Optional cross-coupling for rail-to-rail swingBSSSSABAYYLL11/1/2005 VLSI Design I; A. Milenkovic 9Differential PT Logic (CPL)ABABPT NetworkFABABInverse PT NetworkFFFF=ABAABF=ABBBBAND/NANDAABF=A+BBF=A+BBBOR/NORAAF=A⊕BF=A⊕BBBXOR/XNORAA11/1/2005 VLSI Design I; A. Milenkovic 10CPL Properties• Differential so complementary data inputs and outputs are always available (so don’t need extra inverters)• Still static, since the output defining nodes are always tied to VDDor GND through a low resistance path• Design is modular; all gates use the same topology, only the inputs are permuted.• Simple XOR makes it attractive for structures like adders• Fast (assuming number of transistors in series is small)• Additional routing overhead for complementary signals• Still have static power dissipation problems11/1/2005 VLSI Design I; A. Milenkovic 11CPL Full AdderAABBCinCin!SumSumCout!CoutAABBBB CinCinCinCin11/1/2005 VLSI Design I; A. Milenkovic 12CPL Full AdderAABBCinCin!SumSumCout!CoutAABBBB CinCinCinCin•VLSI Design I; A. Milenkovic •3Sequential Circuits11/1/2005 VLSI Design I; A. Milenkovic 14Sequencing• Combinational logic– output depends on current inputs• Sequential logic– output depends on current and previous inputs– Requires separating previous, current, future–Called state or tokens– Ex: FSM, pipelineCLclkin outclk clk clkCL CLPipelineFinite State Machine11/1/2005 VLSI Design I; A. Milenkovic 15Sequencing Cont.• If tokens moved through pipeline at constant speed, no sequencing elements would be necessary• Ex: fiber-optic cable– Light pulses (tokens) are sent down cable– Next pulse sent before first reaches end of cable– No need for hardware to separate pulses–But dispersion sets min time between pulses• This is called wave pipelining in circuits• In most circuits, dispersion is high– Delay fast tokens so they don’t catch slow ones.11/1/2005 VLSI Design I; A. Milenkovic 16Sequencing Overhead• Use flip-flops to delay fast tokens so they move through exactly one stage each cycle.• Inevitably adds some delay to the slow tokens• Makes circuit slower than just the logic delay– Called sequencing overhead• Some people call this clocking overhead– But it applies to asynchronous circuits too– Inevitable side effect of maintaining sequence11/1/2005 VLSI Design I; A. Milenkovic 17Sequential LogicCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputs11/1/2005 VLSI Design I; A. Milenkovic 18Timing MetricsclockInOutdatastableoutputstableoutputstabletimetimetimeclockDQInOuttsutholdtc-q•VLSI Design I; A. Milenkovic •411/1/2005 VLSI Design I; A. Milenkovic 19System Timing ConstraintsCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsT ≥ tc-q+ tplogic+ tsutcdreg+ tcdlogic≥ tholdT (clock period)11/1/2005 VLSI Design I; A. Milenkovic 20Sequencing Elements• Latch: Level sensitive– a.k.a. transparent latch, D latch• Flip-flop: edge triggered– A.k.a. master-slave flip-flop, D flip-flop, D register• Timing Diagrams– Transparent– Opaque– Edge-triggerDFlopLatchQclk clkDQclkDQ (latch)Q (flop)11/1/2005 VLSI Design I; A. Milenkovic 21Sequencing Elements• Latch: Level sensitive– a.k.a. transparent latch, D latch• Flip-flop: edge triggered– A.k.a. master-slave flip-flop, D flip-flop, D register• Timing Diagrams– Transparent– Opaque– Edge-triggerDFlopLatchQclk clkDQclkDQ (latch)Q (flop)11/1/2005 VLSI Design I; A. Milenkovic 22Latch Design• Pass Transistor Latch•Pros++• Cons––––––DQφ11/1/2005 VLSI Design I; A. Milenkovic 23Latch Design• Pass Transistor Latch•Pros+Tiny+ Low clock load• Cons–Vtdrop– nonrestoring– backdriving– output noise sensitivity– dynamic– diffusion inputDQφUsed in 1970’s11/1/2005 VLSI Design I; A. Milenkovic 24Latch Design• Transmission gate+-DQφφ•VLSI Design I; A. Milenkovic •511/1/2005 VLSI Design I; A. Milenkovic 25Latch Design• Transmission gate+No Vtdrop- Requires inverted clockDQφφ11/1/2005 VLSI Design I; A. Milenkovic 26Latch Design• Inverting buffer+++ Fixes either••–DφφXQDQφφ11/1/2005 VLSI Design I; A. Milenkovic 27Latch Design• Inverting buffer+Restoring+ No backdriving+ Fixes either• Output noise sensitivity• Or diffusion input– Inverted outputDφφXQDQφφ11/1/2005 VLSI Design I; A. Milenkovic 28Latch Design• Tristate feedback+–φφφφQDX11/1/2005 VLSI Design I; A. Milenkovic 29Latch Design• Tristate feedback+Static– Backdriving risk• Static latches are now essentialφφφφQDX11/1/2005 VLSI Design I; A. Milenkovic 30Latch Design• Buffered input++φφQDXφφ•VLSI Design I; A. Milenkovic •611/1/2005 VLSI Design I; A. Milenkovic 31Latch Design• Buffered input+ Fixes diffusion input+ NoninvertingφφQDXφφ11/1/2005 VLSI Design I; A. Milenkovic 32Latch Design• Buffered output+φφQDXφφ11/1/2005 VLSI Design I; A. Milenkovic 33Latch Design• Buffered output+ No backdriving• Widely used in standard cells+ Very robust (most important)-Rather large- Rather slow (1.5 – 2 FO4 delays)- High clock loadingφφQDXφφ11/1/2005 VLSI Design I; A. Milenkovic 34Latch Design• Datapath


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