•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IL08: Pass Transistor LogicDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )www.ece.uah.edu/~milenka/cpe527-05F9/19/2005 VLSI Design I; A. Milenkovic 2Review: CMOS Circuit Styles• Static complementary CMOS - except during switching, output connected to either VDD or GND via a low-resistance path– high noise margins• full rail to rail swing• VOH and VOL are at VDD and GND, respectively– low output impedance, high input impedance– no steady state path between VDD and GND (no static power consumption)– delay a function of load capacitance and transistor resistance– comparable rise and fall times (under the appropriate transistorsizing conditions)• Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes– simpler, faster gates– increased sensitivity to noise9/19/2005 VLSI Design I; A. Milenkovic 3Review: Static Complementary CMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPUN and PDN are dual logic networks……Pull-up network (PUN) and pull-down network (PDN)PMOS transistors onlypull-up: make a connection from VDDto F when F(In1,In2,…InN) = 1NMOS transistors onlypull-down: make a connection from F to GND when F(In1,In2,…InN) = 09/19/2005 VLSI Design I; A. Milenkovic 4Review: OAI22 Logic GraphCABX = !((A+B)•(C+D))BADVDDXXGNDABCPUNPDNCDDABCD9/19/2005 VLSI Design I; A. Milenkovic 5Review: OAI22 LayoutBADVDDGNDCX Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!)9/19/2005 VLSI Design I; A. Milenkovic 6Review: VTC is Data-DependentABF= A • BABM1M2M3M4CintVGS1= VBVGS2= VA –VDS10123012A,B: 0 -> 1B=1, A:0 -> 1A=1, B:0->10.5µ/0.25µ NMOS0.75µ /0.25µ PMOS The threshold voltage of M2is higher than M1due to the body effect (γ)VTn2= VTn0+ γ(√(|2φF| + Vint) - √|2φF|)since VSBof M2is not zero (when VB= 0) due to the presence of CintVTn1= VTn0DDSSweakerPUN•VLSI Design I; A. Milenkovic •29/19/2005 VLSI Design I; A. Milenkovic 7Static CMOS Full Adder CircuitBBBBBBBBAAAAAAAACinCinCinCinCin!Cout!Sum9/19/2005 VLSI Design I; A. Milenkovic 8Static CMOS Full Adder CircuitBBBBBBBBAAAAAAAACinCinCinCinCin!Cout!Sum!Cout= !Cin& (!A | !B) | (!A & !B)Cout= Cin& (A | B) | (A & B)!Sum = Cout& (!A | !B | !Cin) | (!A & !B & !Cin)Sum = !Cout& (A | B | Cin) | (A & B & Cin)Pass Transistor Logic9/19/2005 VLSI Design I; A. Milenkovic 10NMOS Transistors in Series/Parallel• Primary inputs drive both gate and source/drain terminals• NMOS switch closes when the gate input is high• Remember –NMOS transistors pass a strong 0 but a weak 1ABXYX = Y if A and BXYABX = Y if A or B9/19/2005 VLSI Design I; A. Milenkovic 11PMOS Transistors in Series/Parallel• Primary inputs drive both gate and source/drain terminals• PMOS switch closes when the gate input is low• Remember –PMOS transistors pass a strong 1 but a weak 0ABXYX = Y if A and B = A + BXYABX = Y if A or B = A • B9/19/2005 VLSI Design I; A. Milenkovic 12Pass Transistor (PT) LogicABFB0A0BB= A • BF= A • B• Gate is static – a low-impedance path exists to both supply rails under all circumstances• N transistors instead of 2N• No static power consumption• Ratioless• Bidirectional (versus undirectional)•VLSI Design I; A. Milenkovic •39/19/2005 VLSI Design I; A. Milenkovic 13VTC of PT AND GateA0BBF= A•B0.5/0.250.5/0.250.5/0.251.5/0.25012012B=VDD, A=0→VDDA=VDD, B=0→VDDA=B=0→VDDVout, VVin, VPure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static CMOS inverter insertion)9/19/2005 VLSI Design I; A. Milenkovic 14Differential PT Logic (CPL)ABABPT NetworkFABABInverse PT NetworkFFFF=ABAABF=ABBBBAND/NANDAABF=A+BBF=A+BBBOR/NORAAF=A⊕BF=A⊕BBBXOR/XNORAA9/19/2005 VLSI Design I; A. Milenkovic 15CPL Properties• Differential so complementary data inputs and outputs are always available (so don’t need extra inverters)• Still static, since the output defining nodes are always tied to VDDor GND through a low resistance path• Design is modular; all gates use the same topology, only the inputs are permuted.• Simple XOR makes it attractive for structures like adders• Fast (assuming number of transistors in series is small)• Additional routing overhead for complementary signals• Still have static power dissipation problems9/19/2005 VLSI Design I; A. Milenkovic 16CPL Full AdderAABBCinCin!SumSumCout!CoutAABBBB CinCinCinCin9/19/2005 VLSI Design I; A. Milenkovic 17CPL Full AdderAABBCinCin!SumSumCout!CoutAABBBB CinCinCinCin9/19/2005 VLSI Design I; A. Milenkovic 18NMOS Only PT Driving an Inverter•Vxdoes not pull up to VDD, but VDD–VTnIn = VDDA = VDDVx= VDD-VTnM1M2BSD• Threshold voltage drop causes static power consumption (M2may be weakly conducting forming a path from VDDto GND)• Notice VTnincreases of pass transistor due to body effect (VSB)VGS•VLSI Design I; A. Milenkovic •49/19/2005 VLSI Design I; A. Milenkovic 19Voltage Swing of PT Driving an Inverter• Body effect –large VSBat x - when pulling high (B is tied to GND and S charged up close to VDD)• So the voltage drop is even worseVx= VDD-(VTn0+ γ(√(|2φf| + Vx) - √|2φf|))In = 0 → VDDVDDxOut0.5/0.250.5/0.251.5/0.25012300.511.52Time, nsVoltage, VInOutx = 1.8VDSB9/19/2005 VLSI Design I; A. Milenkovic 20Cascaded NMOS Only PTsB = VDDOutM1yM2Swing on y = VDD -VTn1-VTn2xM1B = VDDOutyM2Swing on y = VDD -VTn1C = VDDA = VDDC = VDDA = VDD• Pass transistor gates should never be cascaded as on the left• Logic on the right suffers from static power dissipation and reduced noise marginsx = VDD -VTn1GSGS9/19/2005 VLSI Design I; A. Milenkovic 21Solution 1: Level Restorer• For correct operation Mrmust be sized correctly (ratioed)Level RestorerM1M2A=0MnMrxBOut =1off= 0A=1Out=0on1• Full swing on x (due to Level Restorer) so no static power consumption by inverter• No static backward current path through Level Restorer and PT since Restorer is only active when A is high9/19/2005 VLSI Design I; A. Milenkovic 22Transient Level Restorer Circuit Response01230 100 200 300 400 500Voltage, VTime, psW/Lr=1.75/0.25W/Lr=1.50/0.25W/Lr=1.25/0.25W/Lr=1.0/0.25W/Ln=0.50/0.25W/L2=1.50/0.25W/L1=0.50/0.25node x never goes below VMof inverter so output never switches• Restorer has speed and