1. INTRODUCTION 2. PREPARE THE CADENCE TOOLS 3. VHDL SIMULATION USING NCLAUNCH 4. VHDL SYNTHESIS TO GATE-LEVEL NETLISTCPE/EE 427, CPE 527, VLSI Design I: Tutorial #5, Standard cell design flow and Power Analysis (from vhdl to layout, mu0 processor) Joel Wilder and Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville 1. INTRODUCTION This tutorial steps you through the process of taking a vhdl design, simulating it using NCLaunch, synthesizing it using Build Gates, re-simulating the gate-level netlist, and then performing auto place-and-route to achieve a finished ASIC. Pads can also be added to your design as shown in previous tutorials. Thus, the vhdl-to-ASIC work flow is illustrated. Also, a simple method to estimate power consumption will be explained towards the end. You will perform this work based on the 0.5um AMI nwell process (lambda = 0.30um). 2. PREPARE THE CADENCE TOOLS From your home directory, change directories into your cadence working directory: $ cd cadence Make a directory for lab5 and change into that directory: $ mkdir lab5 $ cd lab5 3. VHDL SIMULATION USING NCLAUNCH First, download the vhdl files you will use for this tutorial: • mu0.vhd -- contains a vhdl description of the mu0 processor (to learn more about mu0 processor visit http://www.ece.uah.edu/%7Elacasa/tutorials/mu0/mu0desc_files/frame.htm ) • tb_mu0.vhd -- testbench for mu0 component Also make sure that you have “cds.lib” and “osu.lib” from the previous lab directory. Now use the following the command to initialize the libraries cp $CDK_DIR/cdssetup/cdsinit .cdsinit Next, start NCLaunch in a terminal window at the unix prompt: $ nclaunch -new What is NCLaunch? NCLaunch is a graphical user interface that helps you manage large design projects and lets you configure and launch your Cadence simulation tools.VLSI Design I, Tutorial 5 NCLaunch is integrated into the Cadence Interleaved Native Compiled Architecture (INCA) and is a component of the SimVision analysis environment. Want to learn more? Read the NCLaunch User Guide; it is intended for customers who want to simulate Verilog, VHDL, or mixed-language designs using the NCLaunch tool. This manual explains the complete functionality of the tool and gives examples of simulating with NCLaunch. In addition, it serves as a reference guide for finding specific details on using NCLaunch. Select Multiple Step in the NCLaunch pop-up window: The first step in the process of compiling the design units is to associate them with libraries. Select Create cds.lib File… in the Open Design Window and then select Save: Page 2 of 17VLSI Design I, Tutorial 5 Select Include default libraries and press OK: Press OK in the Open Design window and you should see: Page 3 of 17VLSI Design I, Tutorial 5 To perform compilation, you should first configure your compiler. In Tools->VHDL Compiler, enable VHDL 93 features: Page 4 of 17VLSI Design I, Tutorial 5 Next, select the design units in the correct order (from the lowest design units to the top level units – i.e., select your testbench file last), and in the NCLaunch toolbar click on the VHDL compile icon (passing over the icon you will see the following text: 'Launch VHDL compiler with current settings'): Page 5 of 17VLSI Design I, Tutorial 5 The status should indicate the successful completion of the compilation process. To perform Elaboration, expand worklib and the design units in it. Select the top level design unit (usually testbench, in our case tb_mu0) and select its entity: Page 6 of 17VLSI Design I, Tutorial 5 Click on the ‘Launch Elaborator with the current selection’ icon on the menu. The status should indicate the successful completion of the elaboration phase. For simulation, expand the Snapshots directory and select the testbench. Then, click on the Simulation icon on the menu to get the simulation environment loaded: The SimVison console and Design Browser windows will appear: Page 7 of 17VLSI Design I, Tutorial 5 In the Design Browser window, select the top level entity: Page 8 of 17VLSI Design I, Tutorial 5 Select the signals you want to inspect: Page 9 of 17VLSI Design I, Tutorial 5 Click on the 'waveform' icon on the menu to bring up the waveform window. In the SimVison console, type run 10000 ns; as shown: Page 10 of 17VLSI Design I, Tutorial 5 Inspect the waveforms to ensure the design is working properly. Other cool options: Click on the 'schematic' icon on the menu to bring up the schematic tracer: Page 11 of 17VLSI Design I, Tutorial 5 4. VHDL SYNTHESIS TO GATE-LEVEL NETLIST Once you know your design is working properly through simulation, you can synthesize your vhdl design into a gate-level netlist in a similar fashion as was done for the verilog design work flow. 1. Create an encounter directory and copy in the technology files (for AMI 0.5um): $ mkdir encounter $ cd encounter $ cp /apps/iit_lib/osu/osu_stdcells/flow/ami05/* . $ cp /home/grad/wilderj/public_html/synopsys/* . (retrieves a script file and a library file) Now you have created the “encounter” folder and filled it with the template files for the AMI 0.5um technology. (identical to what was done in Tutorial 3) You will use the tool Synopsys Design Compiler for logic synthesis. The script file you’ll use with Synopsys is called “compile_dc.tcl”. This file is retrieved as shown above. Now you will open “compile_dc.tcl” in a text editor and modify it according to your accumulator design. This file is a script file for Synopsys and will be executed line by line. To make it easier to modify, all key values are defined in the beginning of the file. Page 12 of 17VLSI Design I, Tutorial 5 So the only modifications will be done in the header of the file. Specifically, you need to change the following four values: my_verilog_files ../mu0.vhd The RTL input file that we want to synthesize. my_toplevel_module mu0 The name of the top-level module in the RTL code. my_clock_pin clk The name of the clock pin in the RTL code. my_clock_freq_MHz 50 Tells PKS to optimize the circuit so that it is capable to operate at least at 100 MHz. Also look for the following line analyze –f vhdl….. And change it to analyze –f verilog…. Since the Synopsys tool needs some initialization files that are installed in a different directory from your current working directory, you need to temporarily re-assign the OSUcells