UAH CPE 427 - Complementary CMOS Logic Gates

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•VLSI Design I; A. Milenkovic •1CPE/EE 427, CPE 527 VLSI Design IComplementary CMOS Logic GatesDepartment of Electrical and Computer Engineering University of Alabama in HuntsvilleAleksandar Milenkovic ( www.ece.uah.edu/~milenka )Static CMOS Logic•VLSI Design I; A. Milenkovic •29/18/2006 VLSI Design I; A. Milenkovic 3CMOS Circuit Styles• Static complementary CMOS - except during switching, output connected to either VDD or GND via a low-resistance path– high noise margins• full rail to rail swing• VOH and VOL are at VDD and GND, respectively– low output impedance, high input impedance– no steady state path between VDD and GND (no static power consumption)– delay a function of load capacitance and transistor resistance– comparable rise and fall times (under the appropriate transistorsizing conditions)• Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes– simpler, faster gates– increased sensitivity to noise9/18/2006 VLSI Design I; A. Milenkovic 4Static Complementary CMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPUN and PDN are dual logic networks……Pull-up network (PUN) and pull-down network (PDN)PMOS transistors onlypull-up: make a connection from VDDto F when F(In1,In2,…InN) = 1NMOS transistors onlypull-down: make a connection from F to GND when F(In1,In2,…InN) = 0•VLSI Design I; A. Milenkovic •39/18/2006 VLSI Design I; A. Milenkovic 5Threshold DropsVDDVDD→PDN0 →CLCLPUNVDD0 →CLVDDVDDVDD→CL9/18/2006 VLSI Design I; A. Milenkovic 6Threshold DropsVDDVDD→ 0PDN0 → VDDCLCLPUNVDD0 → VDD-VTnCLVDDVDDVDD→ |VTp|CLSDSDVGSSSDDVGS•VLSI Design I; A. Milenkovic •49/18/2006 VLSI Design I; A. Milenkovic 7Construction of PDN• NMOS devices in series implement a NAND function• NMOS devices in parallel implement a NOR functionABA • BABA + B9/18/2006 VLSI Design I; A. Milenkovic 8Dual PUN and PDN• PUN and PDN are dual networks– DeMorgan’s theoremsA + B = A • B [!(A + B) = !A • !B or !(A | B) = !A & !B]A • B = A + B [!(A • B) = !A + !B or !(A & B) = !A | !B]–a parallel connection of transistors in the PUN corresponds to a series connection of the PDN• Complementary gate is naturally inverting (NAND, NOR, AOI, OAI)• Number of transistors for an N-input logic gate is 2N•VLSI Design I; A. Milenkovic •59/18/2006 VLSI Design I; A. Milenkovic 9CMOS NANDABA • BAB011101110100FBAAB9/18/2006 VLSI Design I; A. Milenkovic 10CMOS NAND NANDBAF = NAND(A,B)VddF=1B=0GNDA=0VddF=1B=0GNDA=1VddFBGNDAVddF=1B=1GNDA=0VddF=0B=1GNDA=1•VLSI Design I; A. Milenkovic •69/18/2006 VLSI Design I; A. Milenkovic 11CMOS NORA + BAB011001010100FBAABAB9/18/2006 VLSI Design I; A. Milenkovic 12CMOS NORNORBAF = NOR(A,B)VddFBGNDAVddF=1B=0GNDA=0VddF=0B=1GNDA=0VddF=0B=0GNDA=1VddF=0B=1GNDA=1•VLSI Design I; A. Milenkovic •79/18/2006 VLSI Design I; A. Milenkovic 13Complex CMOS GateOUT = !(D + A • (B + C))DABC9/18/2006 VLSI Design I; A. Milenkovic 14Complex CMOS GateOUT = !(D + A • (B + C))DABCDABC•VLSI Design I; A. Milenkovic •89/18/2006 VLSI Design I; A. Milenkovic 15XNOR/XOR ImplementationABA ⊕ BA ⊕ BABXNOR XORA ⊕ BABABA ⊕ B Can you create the stick transistor layout for the lower left circuit? How many transistors in each?9/18/2006 VLSI Design I; A. Milenkovic 16Combinational Logic Cells• CMOS logic cells– AND-OR-INVERT (AOI)– OR-AND-INVERT(OAI)• Example: AOI221 Z = (A*B + C*D + E)’Z = AOI221(A, B, C, D, E)Exercise: Construct this logic cell?• Example: OAI321Z = [(A+B+C)*(D+E)*F]’Z = OAI321(A, B, C, D, E, F)Exercise: Construct this logic cell? ABCDEZAOI221And Or Inverter221•VLSI Design I; A. Milenkovic •99/18/2006 VLSI Design I; A. Milenkovic 17AOI221EGNDZABCDEAVddBCD9/18/2006 VLSI Design I; A. Milenkovic 18Standard Cell Layout MethodologysignalsRoutingchannelVDDGNDWhat logic function is this?•VLSI Design I; A. Milenkovic •109/18/2006 VLSI Design I; A. Milenkovic 19OAI21 Logic GraphCABX = !(C • (A + B))BACijjVDDXXiGNDABCPUNPDNABC9/18/2006 VLSI Design I; A. Milenkovic 20Two Stick Layouts of !(C • (A + B))ABCXVDDGNDXCABVDDGNDuninterrupted diffusion strip•VLSI Design I; A. Milenkovic •119/18/2006 VLSI Design I; A. Milenkovic 21Consistent Euler PathjVDDXXiGNDABC For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same) An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once.9/18/2006 VLSI Design I; A. Milenkovic 22Consistent Euler PathjVDDXXiGNDABCABC An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once.For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)•VLSI Design I; A. Milenkovic •129/18/2006 VLSI Design I; A. Milenkovic 23OAI22 Logic GraphCABX = !((A+B)•(C+D))BADVDDXXGNDABCPUNPDNCDDABCD9/18/2006 VLSI Design I; A. Milenkovic 24OAI22 LayoutBADVDDGNDCX Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!)•VLSI Design I; A. Milenkovic •139/18/2006 VLSI Design I; A. Milenkovic 25Combinational Logic Cells (cont’d)• The AOI family of cells with 3 index numbers or less– X = {AOI, OAI, AO, OA}; a,b,c={2,3}14Total4X222, X333, X332, X322Xabc3X221, X321, X331Xab13X22, X33, X32Xab2X211, X311Xa112X21, X31Xa1Number of Unique CellsCellsCell Type9/18/2006 VLSI Design I; A. Milenkovic 26VTC is Data-DependentABF= A • BABM1M2M3M4CintVGS1= VBVGS2= VA –VDS10123012A,B: 0 -> 1B=1, A:0 -> 1A=1, B:0->10.5µ/0.25µ NMOS0.75µ /0.25µ PMOS The threshold voltage of M2is higher than M1due to the body effect (γ)VTn2= VTn0+ γ(√(|2φF| + Vint) - √|2φF|)since VSBof M2is not zero (when VB= 0) due to the presence of CintVTn1= VTn0DDSSweakerPUN•VLSI Design I; A. Milenkovic •149/18/2006 VLSI Design I; A. Milenkovic 27Static CMOS Full Adder CircuitBBBBBBBBAAAAAAAACinCinCinCinCin!Cout!Sum9/18/2006 VLSI Design I; A. Milenkovic 28Static CMOS Full Adder CircuitBBBBBBBBAAAAAAAACinCinCinCinCin!Cout!Sum!Cout= !Cin& (!A | !B) | (!A & !B)Cout= Cin& (A | B) | (A & B)!Sum = Cout& (!A | !B | !Cin) | (!A & !B & !Cin)Sum = !Cout& (A | B | Cin) |


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