Course Administration Instructor Aleksandar Milenkovic milenka ece uah edu www ece uah edu milenka EB 217 L Mon 5 30 PM 6 30 PM Wen 12 30 13 30 PM http www ece uah edu milenka cpe527 05F Joel Wilder Lab 1 this week CMOS VLSI Design 3rd ed Weste Harris Introduction Design Metrics IC Fabrication Read Chapter 1 IC Fabrication Chapter 3 MOS Transistor Theory Chapter 2 CPE EE 427 CPE 527 VLSI Design I L04 MOS Transistors Theory Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic www ece uah edu milenka www ece uah edu milenka cpe527 05F URL TA Labs Text Review Today 9 6 2005 VLSI Design I A Milenkovic Review Simplified CMOS Inverter Process 2 Review Intra Layer Design Rules cut line Same Potential 0 or 6 Well Different Potential 2 9 Polysilicon 2 10 3 Active Contact or Via Hole 3 3 Metal1 2 2 2 Select 3 4 Metal2 3 p well 9 6 2005 VLSI Design I A Milenkovic 3 9 6 2005 VLSI Design I A Milenkovic Review Inter Layer Design Rule Origins 4 Review Vias and Contacts 1 Transistor rules transistor formed by overlap of active and poly layers 2 Transistors 4 Via Catastrophic error 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 Unrelated Poly Diffusion 2 Thinner diffusion but still working 9 6 2005 VLSI Design I A Milenkovic VLSI Design I A Milenkovic 2 5 9 6 2005 VLSI Design I A Milenkovic 6 1 Outline Introduction Introduction MOS Capacitor nMOS I V Characteristics pMOS I V Characteristics Gate and Diffusion Capacitance Non Ideal IV Effects So far we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current voltage I V relationships Transistor gate source drain all have capacitance I C V t t C I V Capacitance and current determine speed Also explore what a degraded level really means 9 6 2005 VLSI Design I A Milenkovic 7 9 6 2005 MOS Capacitor 8 Terminal Voltages Gate and body form MOS capacitor Operating modes Accumulation Depletion Inversion VLSI Design I A Milenkovic p type body a depletion region b Vgs Vs Vds Vd Source and drain are symmetric diffusion terminals nMOS body is grounded First assume source is 0 too Three regions of operation Cutoff Linear Saturation Vg Vt inversion region depletion region Vgd By convention source is terminal at lower voltage Hence Vds 0 0 Vg Vt Vg Vgs Vg Vs Vgd Vg Vd Vds Vd Vs Vgs Vgd polysilicon gate silicon dioxide insulator Vg 0 Mode of operation depends on Vg Vd Vs c 9 6 2005 VLSI Design I A Milenkovic 9 9 6 2005 nMOS Cutoff VLSI Design I A Milenkovic 10 nMOS Linear No channel Ids 0 Channel forms Current flows from d to s e from s to d Vgs 0 g s d n Vgs Vt Ids increases with Vds Similar to linear resistor Vgd g s Vgd Vgs d n Vds 0 n p type body b n p type body Vgs Vt b g s d n n Vgs Vgd Vt Ids 0 Vds Vgs Vt p type body b 9 6 2005 VLSI Design I A Milenkovic VLSI Design I A Milenkovic 11 9 6 2005 VLSI Design I A Milenkovic 12 2 nMOS Saturation I V Characteristics In Linear region Ids depends on Channel pinches off Ids independent of Vds We say current saturates Similar to current source How much charge is in the channel How fast is the charge moving Vgs Vt g Vgd Vt d Ids s n n Vds Vgs Vt p type body b 9 6 2005 VLSI Design I A Milenkovic 13 9 6 2005 VLSI Design I A Milenkovic Channel Charge Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Gate oxide channel Qchannel Qchannel CV C polysilicon gate W tox n L SiO2 gate oxide good insulator ox 3 9 n gate Vg Cg Vgd drain V source gs Vs Vd channel n n Vds polysilicon gate W tox n p type body p type body L SiO2 gate oxide good insulator ox 3 9 n VLSI Design I A Milenkovic 15 9 6 2005 MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Gate oxide channel Qchannel CV C Cg oxWL tox CoxWL V polysilicon gate W tox n SiO2 gate oxide good insulator ox 3 9 16 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Qchannel CV C Cg oxWL tox CoxWL V Vgc Vt Vgs Vds 2 Vt Cox ox tox gate Vg V Cg Vgd drain source gs Vs Vd channel n n Vds polysilicon gate W tox n p type body p type body 9 6 2005 p type body VLSI Design I A Milenkovic Channel Charge n gate Vg Cg Vgd drain V source gs Vs Vd channel n n Vds p type body 9 6 2005 L 14 L n SiO2 gate oxide good insulator ox 3 9 Cox ox tox gate Vg V Cg Vgd drain source gs Vs Vd channel n n Vds p type body p type body VLSI Design I A Milenkovic VLSI Design I A Milenkovic 17 9 6 2005 VLSI Design I A Milenkovic 18 3 Carrier velocity Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral E field between source and drain v 9 6 2005 VLSI Design I A Milenkovic Charge is carried by e Carrier velocity v proportional to lateral E field between source and drain v E called mobility E 19 9 6 2005 VLSI Design I A Milenkovic Carrier velocity Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral E field between source and drain v E called mobility E Vds L Time for carrier to cross channel Charge is carried by e Carrier velocity v proportional to lateral E field between source and drain v E called mobility E Vds L Time for carrier to cross channel t 9 6 2005 20 t L v VLSI Design I A Milenkovic 21 9 6 2005 VLSI Design I A Milenkovic nMOS Linear I V 22 nMOS Linear I V Now we know Now we know How much charge Qchannel is in the channel How much time t each carrier takes to cross How much charge Qchannel is in the channel How much time t each carrier takes to cross I ds I ds Qchannel t 9 6 2005 VLSI Design I A Milenkovic VLSI Design I A Milenkovic 23 9 6 2005 VLSI Design I A Milenkovic 24 4 nMOS Linear I V nMOS Saturation I V If Vgd Vt channel pinches off near drain Now we know How much charge Qchannel is in the channel How much time t each carrier takes to cross Qchannel t W V Cox Vgs Vt ds Vds 2 L V Vgs Vt ds Vds 2 …